Isolated Partitions in Multi-Core Systems via Mesh Network Control

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Solution Overview

Problem

Conventional multi-core processing systems face inefficiencies in communication and resource utilization, leading to potential corruption or interference between applications running on different processors, and traditional debugging methods are limited in scalability and effectiveness for parallel programming.

Innovation Solution

The system dynamically creates multiple isolated partitions in a multi-core processing system, allowing for flexible configuration of core clusters and virtualization, with features like distributed L2 caches, mesh networking, and run-time partitioning to prevent interference and enable efficient debugging across multiple cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If shared memory and inter-processor interrupts are used for communication among processors, then communication capability is improved, but system cost and efficiency deteriorate due to expensive and inefficient mechanisms

Engineering Contradiction:
Improvecommunication capabilityVSAvoidsystem cost
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system is divided into multiple isolated partitions, each with its own processing resources. This segmentation allows independent operation of partitions while reducing the need for complex inter-processor communication mechanisms, as each partition can operate autonomously with its own memory space and processing units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A partition manager acts as an intermediary layer between applications and physical processing resources. It virtualizes the hardware into isolated partitions, enabling efficient resource allocation and management without requiring expensive shared memory and inter-processor interrupt mechanisms for every interaction.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If processors operate in series, then simplicity is maintained, but productivity deteriorates due to waiting queues and inability to execute independent operations simultaneously

Engineering Contradiction:
Improveprocessor architecture simplicityVSAvoidexecution throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The processor architecture transitions from static sequential execution to dynamic parallel execution through multithreading support. The system can dynamically switch between single-threaded and multi-threaded modes, allowing independent operations to execute simultaneously while maintaining the simplicity of the base processor design.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Multiple processing threads are merged into a single processor core through time-slicing and context switching. This allows the processor to execute multiple independent operations appear to run simultaneously, improving throughput while maintaining the physical simplicity of single-core architecture.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If debugging tools capture state information in multithreading processors, then error analysis capability is improved, but execution of other instructions and applications deteriorates due to halting

Engineering Contradiction:
Improvedebugging capabilityVSAvoidexecution continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The processing system is segmented into isolated partitions, allowing debugging operations to be confined to a single partition. This enables state information capture in one partition without halting execution in other partitions, maintaining productivity while providing precise debugging capability for the targeted partition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A partition manager acts as an intermediary that manages debugging requests. It can pause only the specific partition being debugged while allowing other partitions to continue execution, thus maintaining overall system productivity while enabling precise debugging of individual partitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If applications run on multiple processors without isolation, then resource utilization is improved, but reliability deteriorates due to potential corruption or interference

Engineering Contradiction:
Improveresource utilizationVSAvoidapplication isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system divides processing resources into isolated partitions, each with dedicated memory and processing units. This segmentation allows multiple applications to run simultaneously on different partitions with guaranteed isolation, preventing corruption or interference while maintaining high resource utilization through efficient partition management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each partition is given specific local qualities including isolated memory space, dedicated processing units, and controlled access rights. This local quality assurance ensures that applications running in different partitions cannot interfere with each other, while the partition manager optimizes overall resource utilization by allocating resources to appropriate partitions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240272959A1Systems and methods for creating isolated partitions in a multi-core processing system
Publication Date: 2024.08.15 NXP USA INC
  • US20240272959A1 patent drawing
  • US20240272959A1 patent drawing
  • US20240272959A1 patent drawing

AI summary

Systems and methods for dynamically creating multiple isolated partitions in a multi-core processing system have been described. For example, an illustrative, non-limiting embodiment, an integrated circuit may include: a plurality of routers configured to provide a mesh network among a plurality of muti-cluster tiles (MCTs), where each MCT comprises a plurality of processing cores, and a control circuit coupled to the plurality of routers, where the control circuit is configured to control at least one of the plurality of routers to enable or disable at least a portion of the mesh network to create, among the plurality of processing cores, isolated partitions of processing cores.