Isolated SCR ESD Circuit for Negative Voltage Punch-Through Prevention
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Solution Overview
Problem
Existing semiconductor controlled rectifier (SCR) circuits for electrostatic discharge (ESD) protection face limitations in operating voltage, gain, and reliability, particularly for small feature sizes where the voltage can cause collector-emitter punch through and lateral collector-base avalanche conduction.
Innovation Solution
The SCR design is enhanced by forming a p-type region between the p-type well and buried layer, modifying the doping profile with additional Boron implants, and using a lightly doped p-type well region to prevent punch through and avalanche conduction, while also optimizing the gate and shallow trench isolation regions to reduce electric fields and improve current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional Boron implants are performed to modify the doping profile, then the trigger voltage increases and punch through is prevented, but the manufacturing process complexity increases
Solution Approach 1:
The patent modifies the doping profile by performing additional Boron implants with specific doses and energies to create an optimized concentration distribution in the p-type well region, thereby increasing trigger voltage and preventing punch through without fundamental process changes
Solution Approach 2:
The patent performs preliminary Boron implants during well formation before device fabrication to establish the desired doping profile in advance, preventing punch through issues before they can manifest during operation
2Length of moving object
If the SCR is designed for small feature sizes to improve integration, then the operating voltage causes collector-emitter punch through and lateral collector-base avalanche conduction
Solution Approach 1:
The patent creates regions with different doping concentrations within the SCR structure, specifically a lightly doped p-type well region adjacent to the n-type buried layer and a heavily doped P+ region, to locally manage electric fields and prevent punch through at small feature sizes
Solution Approach 2:
The patent extends the solution into the vertical dimension by forming a p-type well region that reaches toward the n-type buried layer, creating a three-dimensional doping structure that manages electric fields more effectively than planar designs at small feature sizes
3Power
If the operating voltage is increased to improve ESD protection capability, then lateral collector-base avalanche conduction occurs
Solution Approach 1:
The patent introduces a lightly doped p-type well region as an intermediary between the heavily doped P+ region and the n-type buried layer, which mediates the electric field distribution to allow high operating voltages without triggering lateral collector-base avalanche conduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved SCR achieves a higher trigger voltage of 16 V with reduced holding voltage, preventing collector-emitter punch through and avalanche conduction, thus providing effective ESD protection without increasing process complexity.
Implementation Method 1
a lightly doped p-type well region to prevent punch through and avalanche conduction
Implementation Method 2
modifying the doping profile with additional Boron implants, and using a lightly doped p-type well region to prevent punch through and avalanche conduction
Implementation Method 3
optimizing the gate and shallow trench isolation regions to reduce electric fields and improve current paths
Data Source
AI summary
A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.