Isolated Source/Drain Contact Layout for Smaller Semiconductor Cells
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Solution Overview
Problem
The continuous scaling down of semiconductor device dimensions to meet demands for lower power consumption and higher performance poses challenges in process control and complexity, particularly in reducing chip area and metal interconnects for efficient electrical connections between source/drain structures.
Innovation Solution
A contact structure is isolated from the source/drain structure in semiconductor devices, using an isolation layer to electrically connect adjacent source/drain structures through metal lines and vias without additional interconnects, thereby reducing the cell height and chip area by 2% to 6%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional metal interconnects are used to electrically connect adjacent source/drain structures, then electrical connection reliability is improved, but chip area and cell height increase
Solution Approach 1:
The patent extracts and eliminates the need for additional metal interconnects by forming a shared contact structure that directly connects adjacent source/drain structures through the substrate. This removes the harmful element (extra metal interconnects) that was previously needed to achieve electrical connection, thereby reducing chip area while maintaining connection reliability.
Solution Approach 2:
The patent merges the electrical connection function into the substrate itself by forming a shared contact structure that serves as a common electrical pathway. Instead of using separate metal interconnects for each connection, the substrate is modified to provide integrated electrical connectivity between adjacent source/drain structures, reducing the number of discrete components and overall chip area.
2Reliability
If additional metal interconnects are used to electrically connect adjacent source/drain structures, then electrical connection reliability is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex metal interconnect structures from the design by replacing them with a simplified shared contact structure formed in the substrate. This extraction of unnecessary components directly reduces device complexity while preserving the essential electrical connection function through a more streamlined architecture.
Solution Approach 2:
The patent combines multiple electrical connection functions into a single shared contact structure within the substrate. By merging what would have been separate metal interconnect paths into one integrated structure, the device complexity is reduced while maintaining reliable electrical connections between adjacent source/drain structures.
3Area of stationary object
If device dimensions are scaled down to reduce chip area, then manufacturing precision requirements increase
Solution Approach 1:
The patent addresses scaling challenges by transitioning the electrical connection approach from a planar metal interconnect layer to a vertical/shared contact structure within the substrate. This dimensional change allows for reduced chip area without proportionally increasing manufacturing precision requirements, as the connection path is reorganized in a different spatial dimension.
Data Source
AI summary
The present disclosure describes a semiconductor device having a contact structure isolated from a source/drain structure. The semiconductor structure includes a gate structure on a substrate, first and second source/drain (S/D) structures on opposite sides of the gate structure, an isolation layer on the second S/D structure, a third S/D structure adjacent to and separate from the second S/D structure, and a S/D contact structure on the isolation layer and the third S/D structure. The isolation layer separates the S/D contact structure from the second S/D structure.