Isolated Seal Conductor Layout for High-Voltage Semiconductor Chips
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Solution Overview
Problem
The existing semiconductor device with a seal conductor grounded to the semiconductor substrate faces issues with undesirable conduction between metal electrodes and the seal conductor when a voltage is applied, leading to reduced withstand voltage due to electric leakage and discharge.
Innovation Solution
A semiconductor device design where a seal conductor is electrically separated from the semiconductor chip, functional devices, and terminals, and is embedded as a wall in the insulating layer to demarcate regions, thereby suppressing undesirable conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the seal conductor is grounded to the semiconductor substrate, then the seal conductor can provide electrostatic discharge protection and shielding, but undesirable conduction occurs between metal electrodes and the seal conductor when voltage is applied, reducing withstand voltage
Solution Approach 1:
The seal conductor is divided into multiple segments separated by insulating layers, creating electrically isolated sections that can provide shielding and ESD protection locally without creating continuous conduction paths that would reduce withstand voltage between high and low potential terminals
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the seal conductor and the metal electrodes/terminals, allowing the seal conductor to maintain its protective function while preventing direct or parasitic conduction paths that would compromise withstand voltage
2Reliability
If the seal conductor is embedded in interlayer insulating layers to surround active elements, then moisture protection and electrical isolation are improved, but undesirable conduction such as electric leakage and electric discharge occurs between metal electrodes and the seal conductor
Solution Approach 1:
The insulating properties are enhanced locally at critical interfaces where the seal conductor contacts or approaches metal electrodes and terminals, using additional insulating layers or increased insulation thickness in these specific regions to prevent electric leakage while maintaining moisture protection throughout the sealed region
Solution Approach 2:
The sealing structure is extended into the vertical dimension by embedding the seal conductor through multiple insulating layers at different heights, creating a three-dimensional sealed region that improves moisture protection while the layered structure inherently provides multiple insulation barriers against electric leakage
Data Source
AI summary
A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.