Galvanically Isolated Semiconductor Chips for Flashover Prevention

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Solution Overview

Problem

Semiconductor devices with multiple chips face potential differences that can lead to damage due to insufficient insulation, resulting in unreliable and unsafe operation, particularly in applications with varying voltage peaks and static differences.

Innovation Solution

A semiconductor device design featuring a chip carrier with electrically insulating structures between semiconductor chips to galvanically isolate them, maintaining constant physical properties over time and preventing voltage flashovers, using materials like ceramic, glass, or Kapton, and avoiding alkaline earth elements and solvents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor chips are arranged on a chip carrier, then functional versatility and redundancy are improved, but potential differences between chips cause insulation failures and device reliability deteriorates

Engineering Contradiction:

Improvefunctional versatilityVSAvoiddevice reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The chip carrier is segmented into multiple electrically isolated potential domains by introducing electrically insulating structures. These structures divide the chip carrier into first and second potential domains, allowing multiple semiconductor chips to operate at different electrical potentials without causing insulation failures. This segmentation enables functional versatility while maintaining device reliability through proper electrical isolation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Electrically insulating structures serve as intermediary elements between semiconductor chips operating at different potentials. These insulating structures prevent direct electrical contact between chips at different potentials, acting as a mediator that allows multiple chips to coexist on the same chip carrier without causing short circuits or insulation failures, thus improving both versatility and reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If insufficient insulation is used between semiconductor chips, then device complexity is reduced, but voltage peaks cause damage and operational safety deteriorates

Engineering Contradiction:

Improveinsulation structure complexityVSAvoidvoltage peak damage

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent employs thin film electrically insulating structures deposited on the chip carrier surface. These thin films provide sufficient electrical insulation against voltage peaks while maintaining a compact device structure. The thin film approach achieves adequate insulation protection without introducing excessive structural complexity, balancing safety requirements with device simplicity.

Inventive Principle:

Principle #30Flexible shells and thin films

3Adaptability or versatility

If static potential differences exist between chips, then operational flexibility is improved, but insulation breakdown occurs and chip safety deteriorates

Engineering Contradiction:

Improveoperational flexibilityVSAvoidchip safety

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent creates distinct equipotential regions (first and second potential domains) separated by electrically insulating structures. Each semiconductor chip operates within its designated equipotential region, maintaining stable electrical potential differences necessary for operational flexibility while preventing insulation breakdown through proper spatial separation and insulation barriers.

Inventive Principle:

Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Ensures reliable operation by preventing voltage flashovers and maintaining consistent physical properties, reducing the risk of damage and failure in semiconductor devices across different potential domains.

Implementation Method 1

an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other

Methodology Applied

Scientific EffectGalvanic isolation: Electrical Resistance

Data Source

PatentUS11837531B2Semiconductor device with galvanically isolated semiconductor chips

Publication Date: 2023.12.05 INFINEON TECHNOLOGIES AG

AI summary

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.