Isolated Silicon Islands on Bulk Substrates Without Full SOI Wafers
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Solution Overview
Problem
The high cost of manufacturing SOI transistors using traditional methods makes them less competitive with bulk silicon transistors, particularly as the cost per transistor increases with scaled process nodes, hindering the adoption of SOI technology as a mainstream commodity process.
Innovation Solution
A semiconductor structure and method that involves forming fully isolated single-crystalline islands on a bulk semiconductor substrate using shallow trench insulator (STI) regions and buried insulator layers, which reduces manufacturing costs by eliminating the need for expensive entire SOI wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SOI wafer methods are used to create isolated single-crystalline islands, then full isolation and single-crystalline quality are achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent divides the wafer into two functional parts: expensive isolated single-crystalline islands for device fabrication and bulk substrate for mechanical support. This segmentation allows only the necessary regions to have the costly SOI structure, reducing overall manufacturing cost while maintaining isolation quality where needed.
Solution Approach 2:
The patent applies different material qualities to different regions: the island regions have high-quality isolated single-crystalline structure for device performance, while the surrounding bulk substrate maintains mechanical integrity. This local differentiation optimizes cost by providing high isolation quality only where devices are fabricated.
2Reliability
If entire SOI wafers are used, then full isolation is achieved across the wafer, but cost per transistor increases with scaled process nodes
Solution Approach 1:
The patent segments the isolation structure into localized buried insulator layers beneath specific island regions rather than providing isolation across the entire wafer. This reduces the total amount of expensive isolation material and processing required, lowering cost per transistor while maintaining full isolation where devices are actually fabricated.
Solution Approach 2:
The patent applies isolation structures partially - only beneath regions where single-crystalline islands are formed - rather than providing excessive isolation across the entire wafer surface. This partial action approach reduces material and processing costs while achieving the necessary isolation quality for device operation.
Data Source
Figure 1
Figure 1A(1)~1A(2)
Figure 1B(1)~1B(2)
AI summary
A semiconductor structure includes a bulk semiconductor substrate with an original semiconductor surface, a semiconductor island region, a shallow trench insulator (STI) region and a buried insulator layer. The semiconductor island region is formed based on the bulk semiconductor substrate. The STI region surrounds the semiconductor island region. The buried insulator layer is a localized insulator layer under the semiconductor island region, wherein a bottom surface of the semiconductor island region is fully isolated from the bulk semiconductor substrate by the buried insulator layer.