Isolated SPI Interface for High-Speed Battery Pack Data Links
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Solution Overview
Problem
As the number of battery packs in electrical vehicles increases, there is a challenge in communicating precise cell voltage measurements from all battery packs to the micro-controller in a timely manner, necessitating high-speed data communication between micro-controllers and battery management integrated circuit (BMIC) devices.
Innovation Solution
The implementation of an Isolated Serial Peripheral Interface (SPI) protocol with a differential signal using a three-pin signal, including a data signal, a synchronization signal, and a bit frame with equal bit and idle periods, along with decoding and format conversion circuits, enables high-speed data transmission across galvanically isolated interfaces, facilitating efficient communication between BMIC devices and micro-controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If standard SPI protocol is used for communication between BMIC devices and micro-controller, then device compatibility is maintained, but data transmission speed is insufficient for real-time battery management
Solution Approach 1:
The patent modifies the SPI protocol parameters by changing the signal structure from traditional four-wire SPI to a three-wire differential interface. The bit frame structure is altered to include equal bit period and idle period, and the voltage levels are changed to differential signaling (SV+ and SV-), enabling higher transmission speeds while maintaining protocol compatibility
Solution Approach 2:
The patent replaces the traditional electrical SPI interface with a differential signaling system that uses voltage differences rather than ground-referenced signals. This substitution enables galvanic isolation through transformers or optocouplers, improving noise immunity and transmission speed while reducing electromagnetic interference
2Reliability
If galvanic isolation is implemented between battery packs and controller, then noise robustness and safety are improved, but data transmission rate is reduced
Solution Approach 1:
The patent introduces differential signaling as an intermediary between the isolated battery pack side and the controller side. The differential interface circuit translates standard SPI signals to differential signals that can be transmitted through galvanic isolation barriers (transformers or optocouplers) while maintaining high data rates and noise immunity
Solution Approach 2:
The patent implements a periodic bit frame structure with equal bit period and idle period, where each bit is transmitted during the bit period and the line returns to idle state during the idle period. This periodic structure synchronized with the clock signal enables reliable high-speed communication through the galvanically isolated interface
3Adaptability or versatility
If multiple battery packs are connected to single micro-controller, then system integration is improved, but communication timing and data collection efficiency deteriorate
Solution Approach 1:
The patent enables continuous high-speed data transmission from multiple battery packs to the micro-controller using the enhanced Isolated SPI interface. The increased transmission speed allows all battery pack data to be collected within required timeframes, eliminating the timing losses that would occur with sequential communication of multiple packs
Data Source
AI summary
A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.