Isolated SPI Battery Management Interface for High-Speed Pack Data

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As the number of battery packs in electrical vehicles increases, there is a challenge in communicating precise cell voltage measurements from all battery packs to the micro-controller in a timely manner, necessitating high-speed data communication between the micro-controller and battery management integrated circuit (BMIC) devices.

Innovation Solution

The implementation of an integrated circuit device with Isolated Serial Peripheral Interface (SPI) signals, utilizing a differential signal with equal bit and idle periods, and decoding circuits to convert these signals into a three-pin format, enabling galvanic isolation and high-speed data communication between BMIC devices and the micro-controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of battery packs increases to improve battery system capacity, then the battery management system can handle larger energy storage, but the data communication time from all battery packs to the micro-controller increases

Engineering Contradiction:
Improvenumber of battery packsVSAvoiddata communication time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary anti-action by preemptively addressing the communication bottleneck before it becomes a critical issue. The BMIC device performs precise cell voltage measurements and prepares data for transmission in advance, using a buffered approach where data is collected and organized before being sent to the micro-controller. This prevents communication delays from accumulating as more battery packs are added to the system.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent segments the battery management system into distributed BMIC devices, each independently managing a subset of battery packs. Each BMIC device handles its own data collection and communication tasks separately, allowing parallel processing of data from multiple battery packs. This segmentation enables the system to scale to larger numbers of battery packs without proportionally increasing the total communication time, as multiple BMIC devices can simultaneously transmit data to the micro-controller.

Inventive Principle:
Principle #1Segmentation

2Productivity

If standard SPI interface is used for communication between BMIC devices and micro-controller, then the interface is simple and widely compatible, but the data transmission speed is insufficient for real-time monitoring requirements

Engineering Contradiction:
Improvedata transmission speedVSAvoidinterface complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary communication protocol that operates between the standard SPI interface and the micro-controller. The BMIC device uses a modified SPI protocol with extended data widths (16-bit or 32-bit per transaction) and optimized clock timing to achieve higher effective data transmission speeds. This intermediary layer maintains compatibility with standard SPI hardware while enabling faster data transfer through protocol-level optimizations, thus improving productivity without requiring complete redesign of the interface architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12056080B2High speed data transmission in battery management systems with isolated SPI interface
Publication Date: 2024.08.06 STMICROELECTRONICS SRL
  • US12056080B2 patent drawing
  • US12056080B2 patent drawing
  • US12056080B2 patent drawing

AI summary

A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.