Isolated Substrate Memory Cell with Segmented Gates
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Solution Overview
Problem
Prior art non-volatile memory (NVM) cells using a single polysilicon layer face challenges in achieving high memory cell density and efficient erasing, with existing solutions either requiring UV radiation for erasure or using multiple poly layers, which increases space requirements or necessitates two PMOS devices.
Innovation Solution
A non-volatile memory cell design featuring a fully isolated substrate with a large control gate, an intermediate-sized read gate, and a small erase/program gate, all formed from a single polysilicon layer, allowing for electrical erasure and programming through Fowler-Nordheim tunneling, and decoupling the erase/program gate from the read transistor to improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single polysilicon layer is used to define all gates, then device complexity is reduced, but memory cell density and erasing efficiency deteriorate
Solution Approach 1:
The single polysilicon layer is segmented into three distinct gate structures with different sizes and functions: a large control gate for overall control, an intermediate read gate for sensing operations, and a small erase/program gate for charge injection/removal. This segmentation allows each gate to be optimized for its specific function while maintaining the simplicity of a single-layer structure.
Solution Approach 2:
The patent utilizes vertical stacking of the polysilicon gates over the isolated substrate, creating a three-dimensional arrangement where gates are positioned at different heights and lateral positions. This dimensional approach increases functional capacity without requiring additional polysilicon layers.
2Ease of manufacture
If a single polysilicon layer is used, then manufacturing is simplified, but the ability to electrically erase individual cells deteriorates
Solution Approach 1:
The small erase/program gate is specifically designed with localized dimensions and positioning to enable focused electrical erasure of individual memory cells. Its smaller size allows precise voltage application to specific cells without affecting neighboring cells, achieving electrical erasure capability that would be difficult with uniform gate structures.
Solution Approach 2:
The isolated substrate acts as an intermediary between the polysilicon gates and the underlying substrate, enabling electrical erasure through Fowler-Nordheim tunneling. The isolation layers facilitate controlled electric field formation for charge injection and removal while maintaining the single-polysilicon-layer structure.
3Productivity
If gate size is reduced to increase density, then memory cell density improves, but data retention under bias deteriorates
Solution Approach 1:
The three gates are deliberately designed with asymmetric size relationships (large control gate, intermediate read gate, small erase/program gate) rather than uniform dimensions. This asymmetry allows smaller gate sizes for density while the larger control gate provides sufficient coupling to maintain data retention under bias conditions.
Solution Approach 2:
The large control gate serves multiple functions: it controls the floating bulk for charge storage, provides read control through coupling, and maintains data retention under bias through its larger dimensions. This multi-functionality allows smaller read and erase gates without compromising overall reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances memory cell density by reducing size requirements and enabling efficient electrical erasure, while maintaining the advantages of a single poly structure, and improves data retention under bias conditions.
Implementation Method 1
allowing for electrical erasure and programming through Fowler-Nordheim tunneling
Data Source
AI summary
In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate.