Isolated Thermal Interface Layout for High-Voltage Converter Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Aerospace power electronics converters face limitations in efficiency and power-to-weight ratio due to high parasitic inductance in commutation cells, which restricts the increase in switching frequency and operating voltage, leading to heat generation and performance constraints.
Innovation Solution
The design incorporates a power electronics converter with a commutation cell featuring reduced parasitic inductance, achieved by integrating the gate driver circuit within the commutation cell and using a multi-layer planar carrier substrate with optimized electrical connections and thermal management, allowing for higher switching frequencies and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power module topology is used with conventional electrical connections, then device complexity is reduced and ease of manufacture is improved, but parasitic inductance increases and efficiency decreases
Solution Approach 1:
The patent merges the gate driver circuit with the power semiconductor switching elements into an integrated module structure. The gate driver is positioned in direct thermal and electrical proximity to the power devices, eliminating separate connection paths and reducing parasitic inductance. This integration allows simultaneous optimization of both efficiency and complexity.
Solution Approach 2:
The patent transitions from conventional planar electrical connections to a three-dimensional integrated module architecture. Power semiconductor switching elements are arranged vertically with direct bonding to the carrier substrate, and gate drivers are positioned in adjacent vertical spaces, creating compact 3D interconnections that reduce current loop areas and parasitic inductance while maintaining manufacturability.
2Power
If switching frequency is increased to improve power density, then power-to-weight ratio improves, but parasitic inductance causes voltage overshoot and limits further frequency increase
Solution Approach 1:
The integration of gate drivers with power switching elements in direct electrical connection eliminates intermediate connection points, reducing parasitic inductance. This allows higher switching frequencies to be achieved without excessive voltage overshoot, thereby improving power density and power-to-weight ratio while maintaining voltage control reliability.
Solution Approach 2:
The patent optimizes the electrical parameters of the commutation cell by minimizing connection lengths and using low-inductance bonding techniques. The carrier substrate design incorporates optimized trace geometries and direct bonding structures that reduce parasitic inductance values, enabling higher switching frequencies without voltage overshoot limitations.
3Use of energy by moving object
If operating voltage is increased to reduce current and improve efficiency, then use of energy improves, but parasitic inductance increases switching losses and limits voltage increase
Solution Approach 1:
The integrated module structure combines gate drivers and power devices with minimal electrical separation, reducing parasitic inductance in the commutation cell. This reduction in parasitic inductance decreases switching losses, allowing the converter to operate at higher voltages with improved overall efficiency without being penalized by excessive switching losses.
Solution Approach 2:
The patent modifies the electrical parameters of the commutation cell by implementing low-inductance connection topologies and optimized carrier substrate designs. These parameter changes reduce the L di/dt losses during switching transitions, enabling higher operating voltages that improve converter efficiency by reducing resistive losses in the power circuit.
4Temperature
If conventional thermal management is used, then device simplicity is maintained, but heat removal is insufficient and temperature increases
Solution Approach 1:
The patent merges thermal management functionality directly into the module carrier substrate structure. The carrier substrate incorporates integrated heat sinks and thermal pathways that are structurally combined with the electrical connection layers. This integration improves heat removal efficiency by reducing thermal resistance at interfaces while avoiding the need for separate external thermal management components.
Solution Approach 2:
The carrier substrate is designed to perform multiple functions simultaneously: it provides electrical connections between power devices and external circuits, mechanical support for the integrated module, and thermal conduction pathways to heat sinks. This multi-functionality improves heat removal efficiency without increasing overall device complexity, as the same structural elements serve both electrical and thermal management purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances efficiency up to 99% and improves power density, reducing weight and size while effectively managing heat, thus addressing the limitations of existing converters.
Implementation Method 1
a thermal interface layer (TIL) between a heat removal side of the prepackage and the heat sink
Implementation Method 2
an electrical isolation layer between the power semiconductor prepackage and the TIL or between the TIL and the heat sink
Data Source
AI summary
A power electronics converter includes a carrier substrate, and a converter commutation cell including a power circuit. The power circuit includes a power semiconductor switching element included in a power semiconductor prepackage. The power semiconductor prepackage includes a power semiconductor switching element and an electrical connection extending from a terminal of the power semiconductor switching element to an electrical connection side of the power semiconductor prepackage. The power electronics converter includes a heat sink arranged to remove heat from the power semiconductor prepackage, a thermal interface layer arranged between the heat removal side of the power semiconductor prepackage and the heat sink, and an electrical isolation layer arranged between the power semiconductor switching element and the heat sink. A product of a thermal conductivity of the thermal interface layer and a breakdown electric field strength of the electrical isolation layer is greater than or equal to 5 MVW/m2K.