Isolated Transceiver With Concealed Power Nodes
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Solution Overview
Problem
Traditional line transceivers have limited ability to operate and tolerate voltages on bus lines relative to supply and ground connections, leading to communication interruptions or device destruction due to ground potential variations.
Innovation Solution
A powered isolated transceiver with concealed isolated supply and ground nodes, using low voltage devices and a simplified architecture to achieve high common mode performance and robust operation, absorbing ESD/EOS and voltage tolerance stresses through an isolation boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional line transceivers are used with specified input signal range, then device complexity is reduced, but common mode voltage tolerance is limited
Solution Approach 1:
An isolation interface circuit is introduced as an intermediary between the transceiver circuit and the external environment. This isolation circuit acts as a mediator that blocks high common mode voltages and ESD/EOS stresses from reaching the transceiver circuit, while allowing normal signal transmission. The isolation interface includes isolated supply and ground nodes that create an electrical barrier, enabling the transceiver to tolerate voltages beyond its native input range without requiring complex high-voltage protection circuits within the transceiver itself.
2Reliability
If isolation interface circuit is added to provide isolation, then common mode voltage tolerance is improved, but device complexity increases
Solution Approach 1:
The isolation interface circuit is merged with the power supply architecture by using the isolated supply and ground nodes both for powering the transceiver circuit and for establishing the isolation boundary. This dual-use approach integrates the isolation function into the existing power distribution network, eliminating the need for separate isolation protection circuits and reducing overall device complexity despite adding isolation capability.
Solution Approach 2:
The isolated supply and ground nodes serve multiple functions simultaneously: they provide power to the transceiver circuit, establish the isolation boundary for high common mode voltage tolerance, and create reference potentials for signal transmission. This multi-functionality allows a single architectural element to address multiple requirements (powering, isolation, and signaling), reducing the need for additional dedicated components.
3Reliability
If concealed isolated supply and ground nodes are used, then ESD/EOS stress tolerance is improved, but manufacturing complexity increases
Solution Approach 1:
The isolated supply and ground nodes are extracted from the external interface and concealed within the device architecture. By taking out the isolation function from the external pin structure and embedding it internally, the device presents a simple standard interface to manufacturers while maintaining high ESD/EOS tolerance through the hidden isolation boundary. This extraction allows standard manufacturing processes to be used without requiring special handling for isolated pins.
4Ease of manufacture
If low voltage devices are used in simplified architecture, then device cost is reduced, but common mode voltage handling is limited
Solution Approach 1:
The isolation interface circuit serves as an intermediary that protects low voltage devices from high common mode voltages. By placing the isolation boundary between the low voltage transceiver circuit and the high voltage external environment, inexpensive low voltage devices can be used while the isolation interface handles the high voltage stress, achieving both cost reduction and high common mode voltage handling capability.
Data Source
AI summary
A transceiver capable of common mode operating range and output voltage tolerance set by an isolation boundary and not limited by the device type used in the circuitry. The subject technology is a powered isolated transceiver, where the isolated generated supply and ground nodes are concealed and thus do not participate in tests that stress electrostatic discharge (ESD)/electrical overstress (EOS) or voltage tolerance. The architecture of the subject technology has the advantage of extremely high common mode performance and robust performance using low voltage devices and simplified architecture, which in turn provides less capacitive loading, faster operation, less expensive die development, electromagnetic interference (EMI) advantages, and simple active termination. The subject technology includes an isolation architecture that can be used in environments where isolation is used but is also advantageous in systems without the need for isolation.