Isolated VTFET Devices Using SeOI Substrate Cavities
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Solution Overview
Problem
Current CMOS technologies face challenges in forming isolated vertical transport field effect transistors (VTFETs) with efficient electrical isolation between source/drain regions, which affects device performance and integration in logic and memory circuits.
Innovation Solution
The method involves forming vertical fins on a dual insulator semiconductor-on-insulator (SeOI) substrate, creating cavities beneath the fins, and forming n-doped and p-doped bottom source/drain regions with intervening insulator layers for electrical isolation, allowing for the formation of isolated VTFETs with defined volumes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication methods are used, then manufacturing simplicity is maintained, but electrical isolation between source/drain regions is insufficient
Solution Approach 1:
The substrate is divided into isolated regions using deep trenches filled with insulating material. This segmentation physically separates adjacent transistors and their source/drain regions, preventing electrical interference while maintaining independent device operation. The trench isolation structure creates distinct electrical zones without requiring complex process modifications.
Solution Approach 2:
An intermediate insulating layer is introduced between the semiconductor substrate and the source/drain regions. This intermediary layer, positioned at the interface, provides electrical isolation while allowing the fabrication process to continue with standard doping and deposition techniques. The insulating layer acts as a mediator that prevents direct electrical contact between adjacent devices.
2Productivity
If vertical fin structures are formed, then device integration density is improved, but achieving electrical isolation between adjacent fins becomes more difficult
Solution Approach 1:
Electrical isolation is achieved by transitioning from two-dimensional planar isolation to three-dimensional vertical isolation. Deep trenches extend vertically through the substrate beneath adjacent fins, creating isolation in the depth dimension. This allows horizontal fin integration while maintaining vertical electrical separation between devices.
Solution Approach 2:
The isolation structure is nested within the substrate volume, with deep trenches positioned between and beneath the vertical fin structures. The insulating material is embedded in the third dimension, allowing fins to extend upward while isolation structures extend downward and laterally, creating a nested arrangement that provides isolation without reducing integration density.
Data Source
AI summary
A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.