Isolated Well Contact Using Transistor Gate for Low Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor integrated circuits scale, the reduced cross-sectional area of isolated wells under shallow trench isolation (STI) leads to increased resistance and significant voltage drops when high bias is applied, impacting device performance.
Innovation Solution
The use of isolation transistor gates instead of STI geometries to separate well contact diffusions from source and drain diffusions, increasing the cross-sectional area under the isolation and reducing current crowding and voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation (STI) geometries are used to isolate the well, then electrical isolation is achieved, but the cross sectional area of the well under isolation decreases resulting in increased resistance
Solution Approach 1:
The patent transitions from using STI geometries that reduce the well's cross-sectional area to using an isolation transistor gate that maintains a larger cross-sectional area. The isolation transistor gate achieves electrical isolation through field effect control rather than physical constriction, effectively moving from a spatial constraint approach to an electrical control approach.
Solution Approach 2:
The invention changes the isolation mechanism from geometric constraint (STI) to electrical control (transistor gate). By using the transistor gate's electric field to control isolation, the well's cross-sectional area is maintained, thereby reducing resistance while still achieving effective electrical isolation between the well and substrate.
2Object-affected harmful factors
If retrograde well doping is used to reduce well resistance, then resistance at the bottom of the well decreases, but voltage drop remains significant under high bias conditions
Solution Approach 1:
The patent addresses the voltage drop issue by changing from a doping-based resistance reduction approach to a geometry-based approach using the isolation transistor gate. This maintains a larger cross-sectional area for current flow, reducing current crowding and associated voltage drops under high bias conditions.
3Reliability
If the cross sectional area of the well under STI is reduced, then isolation is achieved, but current crowding occurs causing voltage drop
Solution Approach 1:
The invention resolves the current crowding problem by transitioning from STI geometries that physically constrict the well to an isolation transistor gate that provides electrical isolation without geometric constraint. This maintains adequate cross-sectional area for current flow, preventing current crowding while preserving isolation functionality.
Data Source
AI summary
An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.