Isolating Grid Semiconductor Layout for Space-Saving Junction Isolation
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Solution Overview
Problem
Existing semiconductor arrangements face a challenge in providing a space-saving solution with isolated device regions while maintaining effective junction isolation between semiconductor devices of different voltage domains.
Innovation Solution
A semiconductor arrangement is designed with a buried region and an isolating grid that includes a doped region of a first type, forming PN junctions with device regions of a second type, allowing for flexible and space-efficient segmentation of the semiconductor layer into isolated device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each device region includes its designated junction isolation, then effective isolation between device regions is achieved, but space consumption increases
Solution Approach 1:
Multiple device regions share a common isolating grid structure instead of each having separate junction isolations. The isolating grid extends from the first surface to the buried region and electrically isolates multiple device regions simultaneously, reducing total isolation structure area while maintaining effective electrical isolation between regions
Solution Approach 2:
The isolating grid serves multiple functions: it provides junction isolation between device regions, extends to the buried region for enhanced isolation, and can be configured in various patterns (complete grids, partial grids, bridges) to isolate different numbers and arrangements of device regions, making it a universal isolation solution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a space-saving and flexible segmentation of the semiconductor layer into isolated device regions, ensuring effective junction isolation and varying voltage blocking capabilities through the use of an isolating grid and buried region, reducing the risk of unintended current flow.
Implementation Method 1
an isolating grid extending from the first surface to the buried region and including a first region of the first doping type; and device regions of the second doping type adjoining the buried region and isolated from each other by the isolating grid
Data Source
AI summary
A semiconductor arrangement is disclosed. The semiconductor arrangement includes a semiconductor layer having a first surface; a buried region of a first doping type formed in the semiconductor layer spaced apart from the first surface; an isolating grid extending from the first surface to the buried region and including a first region of the first doping type; and device regions of the second doping type adjoining the buried region and isolated from each other by the isolating grid.