Isolation Barrier Fault Detection Using Clock Loss Monitoring
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Solution Overview
Problem
High voltage devices with isolation barriers face risks of electrical shock and equipment damage due to untimely detection of faults, leading to potential electrical overstress events that can cause further system damage.
Innovation Solution
Incorporating a fault detection circuit with a clock signal generator, counters, storage devices, logic gates, and a comparator on a semiconductor die, which monitors the clock signal from a high voltage portion and generates a fault signal when it is no longer received, triggering a controller to interrupt power delivery to the power transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fault detection circuit is added to monitor the clock signal, then the reliability of fault detection is improved, but the device complexity increases
Solution Approach 1:
The device is divided into separate semiconductor dies: a first semiconductor die containing the clock signal generator and a second semiconductor die containing the fault detection circuit. This segmentation isolates the fault detection functionality from the main high voltage circuitry, improving reliability while managing complexity through modular architecture.
Solution Approach 2:
The fault detection circuit continuously monitors the clock signal in advance before faults can propagate. By detecting clock signal interruptions proactively, the system can trigger protective actions before electrical overstress events occur, improving reliability without requiring complex real-time response mechanisms.
2Object-affected harmful factors
If rapid fault detection is implemented to reduce harm and damage, then the safety is improved, but the response time requirement increases the difficulty of detecting and measuring
Solution Approach 1:
The fault detection circuit establishes a feedback mechanism by continuously monitoring the clock signal from the high voltage portion and comparing it against expected parameters. When deviations are detected, the circuit generates fault signals that trigger protective actions. This feedback loop enables rapid automatic response to faults, reducing harmful effects while maintaining manageable detection complexity through systematic signal monitoring.
Data Source
AI summary
A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.