High-Voltage Isolation Capacitor Layout to Limit Leakage Current
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing high-voltage isolation while minimizing leakage current, particularly in mixed analog-digital circuit regions, as thick oxide interlayer insulating films are limited and lower bandgap materials induce undesired leakage current.
Innovation Solution
A method involving the formation of a low bandgap dielectric layer in the high-voltage isolation capacitor region, with specific thickness variations, and its absence under the top metal line, combined with a passivation layer to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick oxide interlayer insulating film is used as the isolation barrier, then high-voltage isolation is improved, but it is hard to increase the high-voltage isolation further
Solution Approach 1:
The patent employs a composite dielectric structure combining a first dielectric layer (thick oxide interlayer insulating film) and a second dielectric layer (low bandgap material) with different bandgap characteristics. This composite structure achieves superior high-voltage isolation performance by leveraging the complementary properties of both materials, overcoming the limitation of using a single thick oxide layer.
Solution Approach 2:
The low bandgap dielectric layer is selectively formed only in the high-voltage isolation capacitor region, while the mixed-signal integrated circuit region maintains its original dielectric structure. This localized application of low bandgap materials provides enhanced isolation precisely where needed without introducing leakage current issues in other circuit regions.
2Reliability
If low bandgap materials are incorporated into the high-voltage isolation capacitors, then high-voltage isolation is improved, but undesired leakage current is induced in the mixed analog-digital circuit region
Solution Approach 1:
The low bandgap dielectric layer is selectively formed only in the high-voltage isolation capacitor region, while the mixed-signal integrated circuit region maintains its original dielectric structure. This localized application of low bandgap materials provides enhanced isolation precisely where needed without introducing leakage current issues in other circuit regions.
Solution Approach 2:
The harmful effect of low bandgap materials (leakage current generation) is isolated by removing or not forming the low bandgap dielectric layer in the mixed-signal integrated circuit region. Only the beneficial high-voltage isolation function is retained in the capacitor region, while the harmful leakage effect is extracted or prevented in other areas.
3Reliability
If the thickness of the thick oxide interlayer insulating film is increased, then high-voltage isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a composite dielectric structure combining a first dielectric layer (thick oxide interlayer insulating film) and a second dielectric layer (low bandgap material) with different bandgap characteristics. This composite structure achieves superior high-voltage isolation performance by leveraging the complementary properties of both materials, overcoming the limitation of using a single thick oxide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enhances high-voltage isolation and minimizes leakage current, ensuring reliable operation in mixed-signal integrated circuits.
Implementation Method 1
low bandgap materials having a bandgap lower than the thick oxide interlayer insulating film are recently incorporated into the high-voltage isolation capacitors
Implementation Method 2
depositing a passivation layer on the low bandgap dielectric layer
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes providing a capacitor region and a circuit region on a substrate; forming a bottom electrode on the capacitor region and forming a bottom metal line on the circuit region; forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line; forming a low bandgap dielectric layer on the inter-metal dielectric layer while removing the low bandgap dielectric layer on the bottom metal line; and forming a top electrode on the low bandgap dielectric layer and forming a top metal line on the inter-metal dielectric layer, wherein the low bandgap dielectric layer is retained under the top electrode, and is absent under the top metal line, such that a distance from the substrate to the top electrode is greater than a distance from the substrate to the top metal line.


