High-Voltage Isolation Capacitor Layout to Minimize Leakage Current
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Solution Overview
Problem
Existing semiconductor devices with high-voltage isolation capacitors face challenges in increasing voltage isolation without inducing undesired leakage current, particularly in mixed analog-digital circuit regions, due to the incorporation of low bandgap materials.
Innovation Solution
A method for manufacturing semiconductor devices involves forming a high-voltage isolation capacitor region with a low bandgap dielectric layer, where the low bandgap dielectric layer is patterned to have specific thickness variations and is not disposed under the top metal line in the mixed-signal integrated circuit region, reducing leakage current by isolating it from the analog-digital circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low bandgap materials are incorporated into high-voltage isolation capacitors to increase voltage isolation, then high-voltage isolation capability is improved, but undesired leakage current is induced in mixed analog-digital circuit regions
Solution Approach 1:
The low bandgap dielectric layer is segmented into a first region positioned over the high-voltage isolation capacitor and a second region positioned over the mixed-signal integrated circuit region, with the second region having smaller thickness than the first region. This segmentation allows the low bandgap material to provide high-voltage isolation where needed while minimizing leakage current in the mixed-signal region.
Solution Approach 2:
Different thicknesses of the low bandgap dielectric layer are applied to different regions: a thicker first low bandgap dielectric layer over the high-voltage isolation capacitor for maximum isolation, and a thinner second low bandgap dielectric layer over the mixed-signal region to reduce leakage. This local quality variation optimizes performance for each specific region's requirements.
2Reliability
If the thickness of the thick oxide interlayer insulating film is increased to improve high-voltage isolation, then isolation capability is improved, but it becomes difficult to achieve further increases in isolation
Solution Approach 1:
The patent employs a composite dielectric structure combining a thick oxide interlayer insulating film with low bandgap dielectric layers. This composite approach leverages the high breakdown voltage of thick oxide while utilizing the lower bandgap materials to enhance isolation capability beyond what thick oxide alone can achieve, overcoming the diminishing returns of simply increasing oxide thickness.
3Ease of manufacture
If the low bandgap dielectric layer is positioned under the top metal line in the mixed-signal region, then manufacturing is simplified, but leakage current increases
Solution Approach 1:
The patent applies different thicknesses of the low bandgap dielectric layer to different regions: a thicker first low bandgap dielectric layer over the high-voltage isolation capacitor and a thinner second low bandgap dielectric layer over the mixed-signal region. This local quality variation optimizes performance for each specific region's requirements while maintaining manufacturability through a systematic deposition and patterning process.
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a high-voltage isolation capacitor region on a substrate, forming a bottom electrode in the high-voltage isolation capacitor region, forming an inter-metal dielectric layer on the bottom electrode, forming a low bandgap dielectric layer on the inter-metal dielectric layer, forming a first hard mask layer on the low bandgap dielectric layer, patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer, depositing a thick metal film on the patterned first hard mask layer and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region, such that the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer.