Monolithic Isolation Capacitor for High Voltage IC Integration
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Solution Overview
Problem
Current methods for integrating high voltage isolation capacitors in integrated circuits face challenges in achieving effective isolation for both power transfer and signaling, particularly in monolithic integrated circuit packages, where existing solutions like optical couplers are limited by data rate and bulkiness, and inductive/capacitive methods struggle with high voltage ratings.
Innovation Solution
A method involving the formation of high voltage rated isolation capacitors on a semiconductor integrated circuit, comprising a sequence of insulating, conductive, and dielectric layers, with specific materials like silicon dioxide and metal conductive layers, allowing for efficient patterning and passivation to achieve electrical isolation between different voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optical couplers are used for signal isolation, then electrical isolation is achieved, but data rate is limited to less than 1 MHz and the device becomes bulky
Solution Approach 1:
The patent replaces optical coupling mechanisms with direct electrical coupling through capacitors. The isolation is achieved through electrical fields rather than optical fields, enabling much higher data rates while maintaining galvanic isolation between different voltage domains.
Solution Approach 2:
The patent changes the isolation mechanism from optical to electrical capacitive coupling. By using capacitors with appropriate voltage ratings and capacitance values, the system achieves both high-speed signal transfer and electrical isolation, overcoming the bandwidth limitations of optical couplers.
2Reliability
If optical couplers are used for signal isolation, then electrical isolation is achieved, but the device becomes bulky to integrate
Solution Approach 1:
The patent merges the isolation capacitor into the integrated circuit package itself, forming a monolithic structure. The capacitor is fabricated using standard IC processing techniques, combining the isolation function with the circuit functionality in a single compact package, eliminating the need for separate bulky optical coupler components.
Solution Approach 2:
The isolation capacitor is nested within the integrated circuit package structure. The capacitor layers are deposited and patterned within the same package that contains the IC, creating a compact nested arrangement where the isolation function is embedded within the circuit architecture rather than being a separate external component.
3Speed
If inductive and capacitive isolation methods are used, then high data rates and isolated power transfer are provided, but high voltage isolation capacitor integration in integrated circuit packages is problematic
Solution Approach 1:
The patent creates a universal isolation capacitor design that can be fabricated using standard integrated circuit processing techniques. The capacitor structure uses conventional materials and deposition methods compatible with IC manufacturing, making it easy to integrate into existing fabrication processes while providing both signal isolation and power transfer capabilities.
Solution Approach 2:
The patent adjusts the voltage rating and capacitance parameters of the isolation capacitor to match the specific requirements of the integrated circuit application. By selecting appropriate dielectric materials and layer thicknesses, the capacitor achieves the necessary high voltage isolation while maintaining compact dimensions suitable for IC package integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of low-cost, high voltage rated capacitors with sufficient capacitance for efficient power and signal transfer between integrated circuit devices connected to different voltage domains, addressing the limitations of existing technologies by providing a compact and effective isolation solution.
Implementation Method 1
depositing a high voltage rated dielectric layer on the first electrically conductive layer
Data Source
AI summary
At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.