Isolation Cells for Monolithic 3D IC Layer Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In monolithic 3D integrated circuits (M3D ICs), the bottom layer cannot be tested separately until both layers are fabricated and I/O pads are available, making defect isolation and yield enhancement challenging due to the integration of interlayer vias (ILVs) and mechanical stress from through-silicon vias (TSVs).
Innovation Solution
The implementation of isolation cells, such as electronic fuses and tri-state flip-flops, allows for the isolation of the bottom layer from the top layer using a bypass structure and ILV pairing with the Munkres algorithm to minimize area overhead and enable localized testing of the bottom layer before complete IC fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithic 3D integration is used to reduce die footprint and improve performance, then integration density and performance are improved, but the bottom layer cannot be tested separately until complete fabrication, making defect isolation difficult
Solution Approach 1:
The patent segments the monolithic 3D IC into isolated testable units by introducing isolation cells between layers. These isolation cells can be selectively activated to separate the bottom layer from the top layer, allowing independent testing of each layer while maintaining the integrated structure during normal operation. This segmentation enables defect isolation without compromising the overall integration density.
Solution Approach 2:
The patent introduces isolation cells as intermediary components between the bottom and top layers. These isolation cells act as mediators that can selectively connect or disconnect the layers during testing. By using these intermediary elements, the system enables separate testing and defect isolation of the bottom layer while maintaining the integrated structure during normal operation.
2Use of energy by moving object
If TSV-based 3D ICs are used for interlayer interconnection, then shorter interconnects and less power consumption are achieved, but significant area overhead and mechanical stress are introduced
Solution Approach 1:
The patent merges the functions of TSVs and ILVs by using ILVs that extend through the entire thickness of the monolithic 3D IC to provide through-silicon connectivity. This combining approach eliminates the need for separate TSV structures, reducing area overhead while maintaining the power consumption benefits of short interconnects. The merged structure also reduces mechanical stress by eliminating the discontinuous TSV architecture.
3Ease of manufacture
If TSV-based 3D ICs are used, then interlayer interconnection is achieved, but die alignment precision is limited to 1 μm, preventing further reduction of 3D contact pitch
Solution Approach 1:
The patent uses the existing high-precision alignment capabilities from the bottom layer fabrication to define the positions of ILVs in the top layer. By copying the alignment references and using the same lithography tools, the system achieves alignment precision much better than 1 μm. This copying approach allows the top layer to be fabricated with the same high precision as the bottom layer, enabling further reduction of 3D contact pitch.
Data Source
AI summary
Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes multiple isolation cells. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops. The integrated circuit also includes a first layer having first and second sets of electronic components, the first set of electronic components being operatively connected to the second set of electronic components via the isolation cells. Further, the integrated circuit includes multiple transmission gates associated with the isolation cells. The integrated circuit also includes a second layer having electrical circuitry operatively connected to the electronic components of the first layer. The electrical circuitry is configured to apply test patterns to the electronic components of the first layer. Further, the electrical circuitry is configured to receive test responses from the electronic components of the first layer through the vias.