Isolation Circuit Re-Clocking for Low-Jitter Data Capture
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Solution Overview
Problem
Signal degradation due to jitter in isolation circuits used in high-speed, high-resolution data capture systems with galvanic isolation degrades the signal-to-noise ratio, particularly at higher input signal frequencies, posing design challenges for isolated analog modules.
Innovation Solution
A circuit design that includes an isolator for isolated signal communication between host-side and converter-side circuits, where a sampling clock generator in the host-side circuit generates a conversion start signal based on a system clock received from the converter-side circuit, and a logic circuit in the converter-side re-clocks the conversion start signal using a low-jitter local clock to mitigate jitter, thereby relaxing jitter specifications and simplifying wide bandwidth and high sampling clock system design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If galvanic isolation is implemented using isolators in high-speed data capture systems, then measurement accuracy and safety are improved by breaking ground loops, but signal-to-noise ratio is degraded due to jitter introduced by the isolator
Solution Approach 1:
The patent introduces an intermediary reclocking stage on the converter side that receives the isolated clock signal and regenerates a clean clock signal to drive the converter. This intermediary stage isolates the jitter from the isolator from affecting the final conversion process, allowing galvanic isolation to be maintained while preserving signal quality.
Solution Approach 2:
The patent segments the clock signal path into distinct isolated and non-isolated portions. The isolated clock signal is used only for timing the conversion start signal through the isolator, while the actual converter operation is driven by a separate clean clock signal generated on the converter side, separating the isolation function from the high-precision conversion function.
2Productivity
If high input signal frequency is used to meet high-speed data capture demands, then productivity is improved, but signal degradation due to jitter is worsened
Solution Approach 1:
The reclocking stage acts as an intermediary that allows high-frequency operation by regenerating clean clock signals at the converter side, enabling high-speed data capture without directly transmitting high-frequency signals through the isolator where they would be susceptible to jitter.
3Measurement precision
If strict jitter specifications are imposed on isolators to maintain signal quality, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces an intermediary reclocking stage on the converter side that receives the isolated clock signal and regenerates a clean clock signal to drive the converter. This intermediary stage isolates the jitter from the isolator from affecting the final conversion process, allowing galvanic isolation to be maintained while preserving signal quality.
Solution Approach 2:
The reclocking stage creates a copy of the clock signal function - instead of using the isolated clock signal directly, a new clean clock signal is generated on the converter side that replicates the timing function without the jitter contamination from the isolator.
Data Source
AI summary
A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.