Semiconductor Isolation Etching to Eliminate Divot Formation
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Solution Overview
Problem
The existing BCD process for manufacturing power devices results in divot formation due to isotropic wet etching of the isolation layer, leading to high leakage current and performance issues.
Innovation Solution
A method is introduced that involves forming a conduction layer with an upper inclined boundary relative to the isolation layer, followed by etching back the isolation layer using wet etching and then the conduction layer using dry etching, ensuring that the top surface of the etched conduction layer is at a lower level than the etched isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If isotropic wet etching is used to etch the isolation layer, then the etching process is simple and fast, but divot formation occurs leading to high leakage current
Solution Approach 1:
The patent divides the etching process into two separate sequential steps: first performing wet etching on the isolation layer, then performing dry etching on the conduction layer. This segmentation allows each etching method to be optimized for its specific target material, preventing divot formation while maintaining etching efficiency.
Solution Approach 2:
The patent inverts the conventional etching sequence by etching the isolation layer first with wet etching, then etching the conduction layer with dry etching. This reversed approach ensures that the conduction layer is etched before the isolation layer is fully removed, preventing divot formation at the interface.
2Reliability
If additional etching steps are added to eliminate divot formation, then leakage current is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the etching of two different layers (isolation layer and conduction layer) into a single integrated process flow using two different etching methods. This merging approach achieves divot elimination without requiring separate process modules, maintaining manufacturing efficiency while improving device reliability.
Solution Approach 2:
The patent changes the etching parameter (etching method) based on the layer being processed: wet etching for the isolation layer and dry etching for the conduction layer. This parameter optimization allows each layer to be etched with the most appropriate method, eliminating divots while keeping the process straightforward.
3Shape
If the conduction layer is etched deeper to match the isolation layer surface, then surface flatness is improved, but more material is removed affecting device performance
Solution Approach 1:
The patent performs preliminary etching of the isolation layer with wet etching before etching the conduction layer with dry etching. This preliminary action creates the proper depth reference, allowing the conduction layer to be etched to the correct depth without over-etching, thus preserving conduction layer material while achieving surface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates divot formation, reduces manufacturing costs, and improves the electrical performance of semiconductor devices by minimizing leakage current.
Implementation Method 1
etching back the isolation layer
Implementation Method 2
etching back the conduction layer
Data Source
AI summary
A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.