Isolation Gate Backside Contacts for Low-Resistance Signal Routing
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Solution Overview
Problem
As standard cells in semiconductor devices become smaller, providing access and reducing resistances within the cells becomes challenging, affecting performance and increasing costs due to parasitic issues and process complexity in routing signals through backside layers.
Innovation Solution
Utilizing isolation gate structures to provide a connection path between signal inputs of active gates and backside metal layers, combining topside and backside routing to reduce resistance and improve performance without significant area or process changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cell size is reduced to increase circuit density, then productivity and area utilization improve, but manufacturing precision and ease of operation deteriorate due to difficulty in providing access to components and increased parasitic effects
Solution Approach 1:
The patent introduces backside contacts that extend through the substrate to the rear surface of the standard cell, adding a vertical dimension (z-axis) to the interconnect architecture. This allows signal and power routes to bypass the crowded topside layout, enabling access to components without increasing lateral footprint and maintaining manufacturing feasibility despite reduced cell dimensions.
Solution Approach 2:
The interconnect system is segmented into topside interconnects for local routing and backside contacts for through-substrate connections. This division separates functions between layers, allowing standard cells to maintain high density on the front side while using the backside for power delivery and signal routing, thus avoiding interference with component access.
2Productivity
If standard cell size is reduced to increase circuit density, then productivity improves, but reliability deteriorates due to increased resistance in metal traces and interfaces
Solution Approach 1:
By routing power and signal connections through the substrate via backside contacts, the patent creates longer but lower-resistance paths that bypass the constrained metal trace geometry on the topside. The vertical through-substrate connections provide additional conduction pathways that reduce overall resistance and improve signal integrity despite smaller cell dimensions.
Solution Approach 2:
The backside contacts act as intermediary structures that mediate between the topside standard cell components and the substrate. These contacts provide low-resistance access points that reduce the burden on topside metal traces, thereby maintaining reliable electrical connections even as cell size decreases and trace dimensions are reduced.
3Reliability
If backside contacts are implemented for signal routing, then resistance is reduced and performance improves, but device complexity increases due to additional routing layers and processes
Solution Approach 1:
The backside contacts serve multiple functions simultaneously: they provide power delivery, signal routing, and reference voltage connections. By consolidating these functions into a single structural element rather than requiring separate dedicated structures for each function, the patent reduces overall device complexity despite adding through-substrate routing capability.
Solution Approach 2:
The patent merges the functions of power supply routing and signal interconnects into the backside contact structure. Rather than implementing separate power grids and signal lines through the substrate, the same backside contact infrastructure supports both functions, simplifying the overall routing architecture and reducing the number of distinct manufacturing steps required.
Data Source
AI summary
A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an isolation gate structure to provide routing between a signal input of an active gate and a backside metal layer. The isolation gate structure includes a metal fill surrounded by gate spacers. The metal fill connects between the topside layers in the device and the backside layer in the device. The metal fill may be connected to the signal input of the active gate through routing either in a topside metal layer or a metal wire placed in a topside insulating layer. The isolation gate structure can be part of any standard cell being placed at a cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with isolation gate structures may provide backside routing connections for adjacent functional cells.