Non-volatile Memory Isolation Latch for Bad Column Exclusion
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Solution Overview
Problem
In non-volatile memory systems, bad columns can skew program-verify fail bit counts, leading to unnecessary programming pulses and potential program failures, as they are currently included in the counting process, which can result in inefficient programming and reduced memory performance.
Innovation Solution
The implementation of isolation latches with indicator bits allows for the selective blocking of program-verify pass/fail bits from bad columns, ensuring that only valid data is counted, thereby preventing the inclusion of faulty columns in the programming process, which can be achieved by splitting data latches into groups with shared or separate isolation latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bad columns are included in the program-verify fail bit count, then the counting process is simple, but the accuracy of program-verify operations deteriorates
Solution Approach 1:
The patent divides the data latch into multiple groups (first plurality and second plurality of data latches) and assigns separate isolation latches to each group. This segmentation allows independent control of bad column exclusion for each latch group, improving measurement precision by accurately excluding only the specific bad columns while maintaining manageable complexity through modular structure.
Solution Approach 2:
The patent introduces isolation latches as intermediary components between the data latches and the fail bit counting process. These isolation latches act as mediators that selectively block or allow pass/fail bits from bad columns to be counted, thereby improving accuracy without requiring complex redesign of the entire counting system.
2Reliability
If separate isolation latches are assigned to each data latch group, then the accuracy of bad column exclusion is improved, but the device complexity increases
Solution Approach 1:
The patent segments the data latch structure into multiple groups, each with its own isolation latch. This segmentation improves reliability by ensuring that bad column exclusion is applied correctly to each group independently, while the modular nature of the segmentation prevents exponential growth in complexity.
Solution Approach 2:
The patent designs the isolation latches and control circuits to perform multiple functions: they not only exclude bad columns from fail bit counting but also enable selective blocking of pass/fail bits and coordinate with common portion control circuits. This multi-functionality reduces the need for separate dedicated components, thereby improving reliability without proportionally increasing device complexity.
3Device complexity
If a shared isolation latch is used for multiple data latch groups, then the device complexity is reduced, but the ability to selectively block bad columns from different groups is limited
Solution Approach 1:
The patent segments the isolation function into separate isolation latches for different data latch groups, enabling each group to independently manage its bad column exclusion. This segmentation provides the adaptability to selectively block bad columns from specific groups while maintaining reasonable device complexity through systematic design.
Solution Approach 2:
The patent implements control circuits in both the individual data latch groups and the common portion that provide feedback mechanisms. These control circuits receive information about bad columns and coordinate the isolation latch states accordingly, enabling selective blocking capability while using feedback to optimize the number of isolation latches needed and reduce overall device complexity.
Data Source
AI summary
A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.