Semiconductor Isolation Layer Stress Management
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Solution Overview
Problem
In semiconductor device manufacturing, the use of polysilazane (PSZ) as a trench gap-fill material leads to tensile stress on trench sides, causing boron dopant migration and increased leakage current in HVNMOS transistors due to thermal-mechanical properties, while HDP oxide layers result in compressive stress and boron depletion.
Innovation Solution
A method involving fluorine ion implantation is performed to protect trench sides, prevent boron migration, and reduce leakage current, which includes ion implantation processes to control threshold voltage, form isolation layers, and use a fluorine-based gas to minimize stress and dopant diffusion, followed by thermal treatment of a polysilazane SOD layer to activate boron without hydrogen interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilazane (PSZ) is used as trench gap-fill material, then trench can be effectively gap-filled, but tensile stress is generated causing boron dopant migration and increased leakage current
Solution Approach 1:
A stress relief layer is introduced as an intermediary between the PSZ gap-fill material and the trench sidewalls. This intermediate layer absorbs or redistributes the tensile stress generated by PSZ, preventing direct stress transmission to the boron-doped sidewalls and thereby reducing boron migration and leakage current.
Solution Approach 2:
The patent modifies the physical and mechanical parameters of the gap-fill system by selecting materials with specific stress characteristics. The stress relief layer is chosen to have complementary stress properties that counterbalance the tensile stress of PSZ, transforming the overall stress state to protect the dopant profile.
2Reliability
If HDP oxide layer is used as trench gap-fill material, then compressive stress is generated and boron migration is reduced, but voids and seams are generated within the trench
Solution Approach 1:
The patent employs a composite gap-fill structure combining multiple materials: PSZ for primary trench filling, HDP oxide for sidewall protection and stress management, and spin-on-glass (SOG) for void elimination. Each material contributes its advantageous properties while compensating for the deficiencies of others, achieving both complete filling and dopant stability.
Solution Approach 2:
The gap-filling process is divided into multiple sequential steps using different materials for different functions. The trench is first filled with PSZ, then additional layers (HDP oxide, SOG) are deposited to address specific issues like voids and stress, creating a segmented multi-layer structure that solves multiple problems simultaneously.
3Manufacturing precision
If ion implantation is performed to control threshold voltage, then device characteristics are improved, but boron dopant is depleted from trench sides increasing leakage current
Solution Approach 1:
The stress relief layer is deposited before the final gap-fill materials to establish a protective barrier in advance. This preliminary action prevents subsequent stress and ion implantation processes from causing excessive boron depletion, counteracting the harmful effects before they fully manifest.
Solution Approach 2:
The patent performs stress relief layer deposition and stress management measures before completing the trench gap-filling and final device processing. This preliminary stress management prepares the structure to better withstand subsequent processing steps that involve ion implantation and thermal treatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces stress on trench sides, minimizes boron migration, and decreases leakage current, enabling the fabrication of stable transistors through selective removal of point defects and boron activation.
Implementation Method 1
performing a fluorine (F) ion implantation process in order to protect trench sides, prevent boron (B) migration and reduce leakage current
Implementation Method 2
thermal treatment of a polysilazane SOD layer to activate boron without hydrogen interference
Implementation Method 3
prevent boron (B) migration
Data Source
AI summary
A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.