Isolation Pillar CFET Layout for Sub-2.5 Nm FET Scaling
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling down field-effect transistors (FETs) beyond 2.5 nm, particularly in reducing device size and eliminating separation bottlenecks between n-type and p-type nanowires or nanosheets in next-generation complementary FET (CFET) devices.
Innovation Solution
The introduction of a dielectric pillar structure through stacked FET cells, such as CFET2 cells, separates gates, source/drain regions, and contacts, enabling electrical connections between front and back side source/drain regions and power rails through metal jumpers and local interconnects, allowing for improved scaling and reduced device area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FET scaling techniques are used, then device size can be reduced, but separation bottlenecks between n-type and p-type nanowires or nanosheets prevent further scaling beyond 2.5 nm
Solution Approach 1:
The patent transitions from planar FET architecture to vertically stacked FET cells, utilizing the third dimension (vertical stacking) to achieve further scaling. By stacking n-type and p-type FETs vertically, the device achieves continued size reduction without the separation bottlenecks that plague traditional lateral scaling approaches.
Solution Approach 2:
The patent divides the FET structure into separate n-type and p-type stacked cells, with each cell containing its own source, drain, and channel regions. This segmentation eliminates the need for physical separation between n-type and p-type nanowires or nanosheets, removing the bottleneck that limits traditional scaling.
2Area of moving object
If device area is reduced through stacking, then scaling efficiency improves, but electrical connections between front and back side source/drain regions become more complex
Solution Approach 1:
The patent introduces intermediate connection structures including metal jumpers and local interconnects that serve as mediators between the front and back side source/drain regions. These intermediary elements simplify the electrical connection path, making it manageable despite the vertical stacking architecture.
Solution Approach 2:
The patent merges multiple electrical connection functions into integrated interconnect structures. The local interconnects and metal jumpers combine routing, connection, and isolation functions, reducing the overall complexity of electrical connections between stacked FET cells.
3Area of moving object
If isolation pillar structures are introduced in stacked FET cells, then device area footprint is reduced by 30-40%, but manufacturing process complexity increases
Solution Approach 1:
The patent incorporates isolation pillar formation as an early step in the manufacturing process, before subsequent FET structure fabrication. By establishing the isolation pillars preliminarily, the patent simplifies later processing steps and enables more efficient manufacturing despite the reduced device footprint.
Solution Approach 2:
The isolation pillar structure serves multiple functions simultaneously: it provides electrical isolation, defines device boundaries, and enables vertical stacking. This multi-functionality reduces the need for additional manufacturing steps, offsetting the increased complexity with process integration efficiency.
Data Source
AI summary
A semiconductor structure includes a first stacked device structure. The first stacked device structure includes a first field-effect transistor disposed on a substrate having a front side and a back side. The first field-effect transistor has a first source/drain region. The first stacked device structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor has a second source/drain region. The first stacked device structure further includes a first front side source/drain contact disposed on the first source/drain region and a first back side source/drain contact disposed on the second source/drain region. The first stacked device structure further includes a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.