Isolation Pillar Work Function Metal Patterning for N-P Spaces
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Solution Overview
Problem
In integrated circuits, the challenge lies in patterning work function metals for active nanostructure transistor devices with closely spaced field effect transistors, where traditional methods face issues with overetching and mask edge placement errors due to the small distances between adjacent nanostructures, leading to potential damage or inoperability of devices.
Innovation Solution
The implementation of an isolation pillar with a unitary, wider upper portion extending above the active nanostructures, which creates a discontinuity in the metal layer to prevent overetching and allows for precise placement of the mask edge, enabling the deposition of different work function metals on adjacent nanostructures without exposing the incorrect one.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional patterning methods are used for closely spaced FETs, then manufacturing process is simpler, but overetching occurs and mask edge placement errors increase leading to device damage
Solution Approach 1:
An isolation pillar is introduced as an intermediary structure between adjacent active nanostructures. This pillar serves as a physical barrier and etch stop layer that prevents overetching from affecting neighboring structures. The pillar includes a lower portion in the space between nanostructures and an upper portion extending above them, creating a discontinuity in metal layers that blocks etch propagation while maintaining manufacturing feasibility.
2Productivity
If feature sizes of FETs are reduced to increase density, then IC density increases, but electrostatic issues and mobility degradation worsen
Solution Approach 1:
The gate structure transitions from planar to three-dimensional gate-all-around configuration where the gate wraps around the channel in multiple dimensions. This provides superior electrostatic control by increasing the gate's control surface area around the channel, enabling effective control even at scaled dimensions. The isolation pillar also extends in the vertical dimension above the nanostructures to prevent lateral overetching.
3Manufacturing precision
If different work function metals are deposited on adjacent nanostructures, then threshold voltage control improves, but overetching removes incorrect metal and exposes the other nanostructure
Solution Approach 1:
The isolation pillar is formed in advance before metal deposition and patterning steps. This preliminary structure serves as a pre-positioned etch stop that prevents overetching from exposing adjacent nanostructures. By having this protective structure in place beforehand, the process allows for precise metal patterning with different work function metals on adjacent structures without the risk of etch-induced damage or incorrect metal removal.
Data Source
AI summary
A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.