Isolation Pillar Layout for Stacked FET Channel Width Control
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Solution Overview
Problem
Current semiconductor technologies face challenges in further scaling down field-effect transistors (FETs) beyond 7 nm, particularly in achieving smaller sizes and more efficient control of channel widths in stacked device structures, which is essential for improved performance and density in integrated circuits.
Innovation Solution
The formation of isolation pillar structures with varying widths between stacked device structures allows for closer placement and controlled channel widths of FETs, enabling flexible n-to-p ratios and improved scaling by using a combination of etching processes and dielectric material filling to create fork-like shapes that adjust active region areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET scaling techniques are used, then device size is reduced, but control over channel widths and device performance deteriorates
Solution Approach 1:
The isolation structure is segmented into multiple portions (first isolation portion, second isolation portion, third isolation portion) with different widths. Each portion independently controls the channel width for specific devices, enabling precise control of channel dimensions while maintaining compact overall device size. The first isolation portion controls first and second devices, the second isolation portion controls third and fourth devices, and the third isolation portion controls fifth and sixth devices, allowing differentiated channel width control across the device array.
Solution Approach 2:
Different portions of the isolation structure have different widths tailored to the specific control needs of adjacent devices. The first isolation portion has a width that controls channel widths for first and second devices, while the second isolation portion has a different width for controlling third and fourth devices. This local customization of isolation structure dimensions enables precise control over channel widths for each device group without compromising overall device miniaturization.
2Area of stationary object
If stacked device structures are placed closer together, then area utilization improves, but isolation and control between devices becomes more difficult
Solution Approach 1:
The isolation structure is divided into multiple segmented portions positioned at different locations between stacked devices. These segmented isolation portions (first, second, and third isolation portions) are strategically placed to provide electrical isolation and mechanical support between closely-spaced stacked devices. The segmentation allows each isolation portion to be independently sized and positioned, enabling effective isolation even when devices are placed at minimal spacing while maintaining simple fabrication processes.
Data Source
AI summary
A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.