Isolation Recess Depth Control in 3D-NAND MOS Regions
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Solution Overview
Problem
Current 3D-NAND processes require different voltage levels for HVMOS, LVMOS, and LLVMOS transistors, leading to varying junction depths and recess requirements in isolation structures, which complicates the fabrication process.
Innovation Solution
A method for fabricating semiconductor devices that involves forming a first recess and a second recess in isolation structures with different depths, where the first recess is deeper than the second recess, by performing ion implantation on the first isolation structure before etching back to enhance the etching rate and achieve the desired depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different voltage levels are used for HVMOS, LVMOS, and LLVMOS transistors, then device functionality is improved, but fabrication process complexity increases due to varying junction depths and recess requirements
Solution Approach 1:
The patent applies local quality by performing ion implantation selectively on the first isolation structure (corresponding to HVMOS region) to modify its etching characteristics, while leaving the second isolation structure (corresponding to LVMOS/LLVMOS region) unmodified. This localized modification enables different etching rates in different regions, allowing simultaneous formation of recesses with different depths using a single etching process, thus maintaining device functionality while simplifying the fabrication process
Solution Approach 2:
The patent changes the physical-chemical parameters of the first isolation structure through ion implantation, specifically modifying its crystal lattice structure and etching rate. By controlling the ion implantation dose and energy, the patent achieves precise control over the etching rate difference between the two isolation structures, enabling the formation of recesses with different depths (first recess deeper than second recess) to satisfy the junction depth requirements of different transistor types
2Reliability
If deeper recesses are formed to satisfy HVMOS junction depth requirements, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by performing ion implantation on the first isolation structure before the etching process. This pre-treatment modifies the etching characteristics of the first isolation structure in advance, ensuring that during the subsequent etching process, the first recess will be formed to the required deeper depth while the second recess forms to a shallower depth. This preliminary modification simplifies the etching process control and improves manufacturing precision by making the etching rates predictable and controllable
Solution Approach 2:
The ion implantation process acts as an intermediary that mediates between the requirement for different recess depths and the single etching process. By introducing this intermediate step, the patent creates a controlled difference in etching rates between the two isolation structures, enabling precise control over the final recess depths without requiring multiple etching steps or complex process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous formation of recesses with different depths, satisfying the junction depth requirements of various transistors and improving device performance by optimizing the structure characteristics.
Implementation Method 1
performing ion implantation on the first isolation structure; the bombardment effect of the ion implantation process on the first isolation structure can cause the crystal lattice of the first isolation structure to be scattered
Data Source
AI summary
A semiconductor device includes a first isolation structure corresponding to a first device region of a substrate and including a first insulating layer in a first isolation groove of the first isolation structure, and a second isolation structure corresponding to a second device region of the substrate and including a second insulating layer in a second isolation groove of the second isolation structure. The first insulating layer comprises ions.