Isolation Recess Depth Tuning for Multi-Voltage 3D-NAND MOS
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Solution Overview
Problem
Current 3D-NAND processes require different voltage levels for HVMOS, LVMOS, and LLVMOS transistors, resulting in varying junction depths and structural characteristics, necessitating the formation of recesses with specific depth differences to meet device demands.
Innovation Solution
A method for fabricating semiconductor devices involves forming a first recess with a greater depth than a second recess by performing ion implantation on isolation structures before etching, which increases the etching rate of the first recess, allowing it to achieve the required deeper junction depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed on the first isolation structure before etching, then the etching rate of the first isolation structure increases and the first recess achieves greater depth, but the process complexity increases
Solution Approach 1:
Ion implantation is performed on the first isolation structure before the etching step to modify its properties in advance. This preliminary action increases the etching rate of the first isolation structure, enabling the first recess to be formed with greater depth than the second recess during the subsequent etching process, thereby achieving precise control over differential recess depths.
2Adaptability or versatility
If different voltage levels are used for HVMOS, LVMOS, and LLVMOS transistors, then device functionality is improved, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies different treatments to different regions: ion implantation is performed only on the first isolation structure (corresponding to HVMOS region requiring deeper junction), while the second isolation structure (corresponding to LVMOS/LLVMOS regions) remains untreated. This local differentiation enables each device type to have the appropriate junction depth for its voltage requirements, maintaining device versatility while managing structural complexity through region-specific processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the first recess is formed with a greater depth than the second recess, satisfying the structural and performance demands of high and low voltage devices, thereby enhancing device performance.
Implementation Method 1
performing ion implantation on the first isolation structure; the bombardment effect of the ion implantation process on the first isolation structure can cause the crystal lattice of the first isolation structure to be scattered
Data Source
AI summary
A semiconductor device and a method for fabricating the same are disclosed. A substrate including a first device region and a second device region is provided. A first isolation structure is formed in the substrate of the first device region and a second isolation structure is formed in the substrate of the second device region. Ion implantation on the first isolation structure is performed. The first isolation structure and the second isolation structure are etched back to form a first recess in the first isolation structure and a second recess in the second isolation structure.