Isolation Strip Stack for Denser GAA Semiconductor Structures

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Solution Overview

Problem

Conventional semiconductor manufacturing processes, particularly in lithography, face constraints due to the need for reserved space for photolithography, limiting the size and density of semiconductor structures and devices.

Innovation Solution

The integration of high-k isolation segments and inner spacers in the gate all around (GAA) transistor manufacturing process allows for reduced space requirements between gate structures, enabling smaller device sizes and increased active areas, thereby enhancing device speed without damaging source/drain structures during processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional lithography processes are used with reserved space between structures, then photolithography can be performed, but device size is constrained and density is reduced

Engineering Contradiction:

Improvedevice densityVSAvoidspace between gate structures

Core Design Contradiction:

ProductivityVSLength of moving object

Solution Approach 1:

The isolation structure is segmented into two distinct parts: a low-k isolation strip at the bottom and a high-k isolation strip on top. This segmentation allows each layer to serve different functions - the low-k layer provides electrical isolation while the high-k layer provides mechanical protection and enables closer spacing, thereby reducing the overall space requirement between gate structures and increasing device density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs a composite isolation structure combining two dielectric materials with different properties - low-k material for electrical isolation and high-k material for mechanical support and enhanced isolation. This composite approach allows the structure to achieve both electrical performance and spatial efficiency, enabling reduced pitch and higher device density

Inventive Principle:

Principle #40Composite materials

2Productivity

If space between gate structures is reduced to increase density, then device density increases, but source/drain structures may be damaged during processing

Engineering Contradiction:

Improvedevice densityVSAvoidsource/drain structure integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The low-k isolation strip is formed first to establish the base isolation structure, followed by the formation of the high-k isolation strip on top. This preliminary action of creating the protective high-k layer before subsequent processing steps prevents side-etching damage to source/drain structures while allowing reduced spacing between gates, thus maintaining both high density and structural reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The high-k isolation strip acts as a protective cushion or barrier layer that prevents harmful etching effects from reaching the source/drain structures during manufacturing processes. This beforehand protection enables the gate structures to be placed closer together without compromising the integrity of adjacent sensitive structures

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12051693B2Method for manufacturing semiconductor structure with isolation strips

Publication Date: 2024.07.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.