Semiconductor Isolation Structure With Multi-Layer CPO Oxide Liner
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA transistor fabrication techniques face challenges in maintaining the integrity of the oxide liner in the CPO feature during the replacement gate process, leading to potential damage and subsequent issues like metal gate protrusion and short circuits due to reduced etching selectivity and surface curvature profiles.
Innovation Solution
Implementing a multi-layer CPO feature with an oxide material positioned at the bottom portion to protect it from exposure during the replacement gate process, combined with a dielectric dummy layer to enhance etching contrast and maintain the integrity of the isolation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer oxide liner is used in the CPO feature, then the structure is simple and manufacturing is easier, but the oxide liner is damaged during the replacement gate process leading to metal gate protrusion and short circuits
Solution Approach 1:
The single-layer oxide liner is divided into multiple oxide liner layers (first oxide liner layer and second oxide liner layer) with different functions. The first oxide liner layer suppresses charge accumulation at the n-type well and p-type well boundary, while the second oxide liner layer protects against damage during the replacement gate process. This segmentation allows each layer to be optimized for its specific purpose, resolving the contradiction between manufacturing simplicity and reliability.
Solution Approach 2:
The oxide liner is constructed as a composite structure with multiple layers of oxide material. This composite approach combines the charge suppression function of the first oxide layer with the protective function of the second oxide layer, achieving both reliability (integrity during replacement gate) and maintaining ease of manufacture through a systematic multi-layer design.
2Adaptability or versatility
If the oxide liner is exposed during the replacement gate process, then the etching selectivity is reduced, but this leads to surface curvature profiles and potential short circuits
Solution Approach 1:
The multi-layer oxide liner structure is prepared in advance before the replacement gate process. The second oxide liner layer is specifically designed to remain intact during the replacement gate process, preventing exposure of the underlying structures. This preliminary preparation ensures that the etching selectivity is maintained and uniform nanostructure surfaces are achieved throughout the manufacturing process.
3Device complexity
If the CPO feature uses a simple oxide liner structure, then the fabrication process is simpler, but it cannot prevent metal gate protrusion and short circuits
Solution Approach 1:
The CPO feature's oxide liner is segmented into multiple functional layers. The first oxide liner layer addresses charge accumulation suppression, while the second oxide liner layer provides protection during replacement gate and prevents metal gate protrusion. This segmentation increases device complexity slightly but dramatically improves reliability by preventing short circuits through the coordinated function of multiple specialized layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures uniformity of nanostructure surfaces and gate profiles, preventing damage to the oxide liner and reducing the risk of short circuits, thereby enhancing device performance and reliability.
Implementation Method 1
a first dielectric layer that contains oxygen and is directly above a boundary between an n-type well and a p-type well, wherein the first dielectric layer suppresses accumulation of charges
Implementation Method 2
depositing a first dielectric layer in the trench, depositing a second dielectric layer in the trench
Data Source
AI summary
A method of the present disclosure includes forming a fin-shaped structure protruding from a substrate, depositing an isolation feature on sidewalls of the fin-shaped structure, forming a dummy gate stack over a portion of the fin-shaped structure, removing a portion of the dummy gate stack to form a trench exposing the portion of the fin-shaped structure, recessing the portion of the fin-shaped structure to extend the trench downward below a top surface of the isolation feature, depositing a first dielectric layer in the trench, recessing the first dielectric layer, such that a topmost portion of the first dielectric layer is below the top surface of the isolation feature, after the recessing of the first dielectric layer, depositing a second dielectric layer in the trench, the first and second dielectric layers including different material compositions, and replacing an unremoved portion of the dummy gate stack with a metal gate structure.