Isolation Structure Layout for Thermally Stable GAA FinFET Stacks
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to form superlattice structures on a substrate without causing thermal damage to the semiconductor layer, which is essential for high-performance FETs, as high-temperature processing can lead to structural degradation.
Innovation Solution
A method is developed to form superlattice structures on a sacrificial substrate with embedded isolation structures, allowing for high-temperature processing before flipping the stack and removing the sacrificial substrate, thus preventing thermal damage to the semiconductor layer. This involves forming an etch stop layer, superlattice structure, channel isolation layer, and bi-layer isolation structure, followed by etching and forming fin structures and gate-all-around structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature processing is applied to form superlattice structures, then the superlattice structures can be successfully formed, but thermal damage occurs to the semiconductor layer causing structural degradation
Solution Approach 1:
The semiconductor layer is formed on the substrate before the superlattice structure. This preliminary formation allows the semiconductor layer to be in place and protected during subsequent high-temperature superlattice formation processes, preventing thermal damage while enabling successful superlattice structure formation.
Solution Approach 2:
The substrate acts as an intermediary between the heating process and the semiconductor layer. By conducting the high-temperature processing through the substrate, the heat is distributed and controlled, allowing superlattice formation without directly exposing the semiconductor layer to extreme temperatures that would cause thermal agglomeration.
2Ease of manufacture
If the substrate is removed early to access the semiconductor layer, then further processing becomes easier, but thermal damage risks increase during superlattice formation
Solution Approach 1:
The semiconductor layer is formed preliminarily on the substrate before superlattice formation. This sequencing allows the substrate to remain in place during high-temperature processing, protecting the semiconductor layer while still enabling subsequent processing steps to be performed on the complete structure.
Solution Approach 2:
Instead of removing the substrate first and then forming structures (which would expose the semiconductor layer to damage), the invention inverts the sequence: the substrate remains in place during superlattice formation, and only after the temperature-sensitive superlattice is formed is the substrate removed. This reversal protects the semiconductor layer from thermal damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-performance FETs with improved reliability by preventing thermal agglomeration and maintaining the structural integrity of the semiconductor layer, enhancing device performance and manufacturing efficiency.
Implementation Method 1
forming superlattice structures on a sacrificial substrate with embedded isolation structures, allowing for high-temperature processing before flipping the stack and removing the sacrificial substrate, thus preventing thermal damage to the semiconductor layer
Data Source
AI summary
A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.