Isolation Structure Layout for GAA Transistor Leakage Control
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Solution Overview
Problem
Existing multi-gate device fabrication techniques face challenges in semiconductor IC dimensions scaling down, leading to current leakage and performance degradation in multi-gate MOSFETs like GAA transistors.
Innovation Solution
A method for forming a semiconductor device with a fin-shaped structure, including a base fin structure and a stack of channel layers, where an isolation feature is formed on the side of the base fin structure, and a gate spacer is deposited over a dummy gate stack. The sacrificial layers are selectively removed to release channel members, and an isolation structure is formed to mitigate current leakage and prevent latch-up issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate device fabrication is scaled down to smaller dimensions, then production efficiency increases and costs decrease, but current leakage and performance degradation occur
Solution Approach 1:
The isolation structure is segmented into multiple functional zones: a first isolation region extending between adjacent fin bases to prevent lateral current leakage, and a second isolation region extending between the first isolation structure and the fin base to prevent latch-up. This segmentation allows each zone to address specific leakage mechanisms independently, maintaining device reliability at scaled dimensions.
Solution Approach 2:
The isolation structure acts as an intermediary element between adjacent fin bases and between the substrate and active device regions. By introducing this intermediate isolation layer, current leakage paths are blocked without directly modifying the fin base or channel structure, thus preventing performance degradation while maintaining scaled dimensions.
2Reliability
If gate structure surrounds channel regions in multi-gate devices, then gate control is improved and off-state current is reduced, but fabrication complexity increases
Solution Approach 1:
The isolation structure is formed preliminarily before the multi-gate device fabrication process begins. By pre-establishing the isolation regions between adjacent fin bases, subsequent fabrication steps can proceed without additional complexity, as the isolation framework is already in place to guide and protect the channel formation process.
Solution Approach 2:
The isolation structure applies different isolation strategies at different locations: the first isolation region addresses lateral leakage between adjacent fins, while the second isolation region addresses vertical latch-up prevention. This localized approach optimizes gate control in specific regions without unnecessarily complicating the entire device structure.
Data Source
AI summary
A method includes forming a stack of channel layers and sacrificial layers over a fin base, forming an isolation feature adjacent to the fin base and the stack, forming a dummy gate structure over the stack and the isolation feature, and forming a source/drain trench in the fin base and exposing sidewalls of the sacrificial layers. The sacrificial layers include a top portion and a bottom portion. The method further includes removing the top portion to form a top opening and the bottom portion to form a bottom opening, depositing a dummy layer in the top and bottom openings, selectively and partially recessing the dummy layer to form inner spacer recesses, forming inner spacer features, forming a source/drain feature, and replacing the dummy gate structure and the dummy layer in the top opening but not the dummy layer in the bottom opening with a metal gate structure.