Isolation Device Common-Mode Transient Immunity Circuit
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Solution Overview
Problem
Isolation devices face challenges in maintaining high common-mode transient immunity, leading to noise and glitches during common-mode transient events, which can degrade signal quality and introduce errors in high-speed applications.
Innovation Solution
The implementation of a common-mode transient detection circuit and rejection circuit in parallel with the amplifier and demodulator, which detects current through a clamp to identify common-mode transient events and temporarily blocks the demodulator output to prevent glitches, thereby maintaining signal integrity without introducing propagation delay or degrading signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation devices are used to protect low-voltage sections from high-voltage sections, then electrical isolation and signal transmission are achieved, but common-mode transient immunity is reduced leading to noise and glitches
Solution Approach 1:
The isolation device is segmented into multiple functional blocks: a first circuit block, a second circuit block, a detection circuit block, and a rejection circuit block. Each block performs a specific function, allowing the system to maintain isolation while adding transient detection and rejection capabilities without compromising the core isolation function.
Solution Approach 2:
An isolation barrier is introduced as an intermediary element between the first and second circuit blocks. This barrier physically separates the circuits while allowing signal transmission, and the detection circuit monitors the intermediary coupling capacitor to detect transient events before they affect the output.
2Object-affected harmful factors
If common-mode transient detection and rejection circuits are added in parallel, then common-mode transient immunity is enhanced, but device complexity increases
Solution Approach 1:
The detection circuit and rejection circuit are merged into a coordinated system where the detection circuit identifies transients and the rejection circuit responds by blocking affected signals. These circuits are integrated with the existing isolation device structure, sharing components like the coupling capacitor and coordinating their operation to provide transient immunity without requiring entirely separate systems.
Solution Approach 2:
The detection circuit performs preliminary detection of common-mode transients before they can significantly degrade signal quality. By detecting voltage changes across the coupling capacitor in advance, the system can prepare the rejection circuit to block affected signals, preventing glitches rather than correcting them after occurrence.
3Reliability
If demodulator output is temporarily blocked to prevent glitches, then signal integrity is maintained, but propagation delay is introduced
Solution Approach 1:
The rejection circuit operates periodically based on transient detection events rather than continuously blocking signals. When the detection circuit identifies a common-mode transient, the rejection circuit temporarily blocks the demodulator output for a specific duration, then resumes normal operation. This periodic blocking approach maintains signal integrity during transients while minimizing overall propagation delay.
Data Source
AI summary
Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.