Isolation Trench Air Sidewalls for Low-Capacitance Semiconductor Structures
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Solution Overview
Problem
The increase in parasitic capacitance between adjacent conductive structures in semiconductor devices due to reduced distance leads to performance deterioration, and traditional fabrication processes of air sidewalls can damage regions other than the array region, exposing electronic devices and reducing product yield.
Innovation Solution
A method involving the formation of a to-be-etched path layer on the sidewall of an isolation trench, followed by a flat surface creation and sequential removal to protect the peripheral region, allowing for the formation of a high-quality protective material layer that prevents damage during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fabrication processes are used to form air sidewalls, then parasitic capacitance between conductive structures can be reduced, but dielectric layers in peripheral regions are damaged and electronic devices are exposed
Solution Approach 1:
The patent divides the substrate into array region and peripheral region, and applies different fabrication processes to each region. The array region undergoes the air sidewall formation process while the peripheral region is protected through selective masking and sequential removal steps, thus resolving the contradiction between reducing parasitic capacitance and protecting peripheral devices
Solution Approach 2:
The patent performs preliminary actions by forming a protective material layer on the peripheral region before the etching process, and creating a to-be-etched path layer on the isolation trench sidewall. These preliminary structures enable selective removal of material only in the array region while preserving the peripheral region, thus preventing damage to peripheral devices
2Productivity
If distance between adjacent conductive structures is decreased to improve integration, then device integration is improved, but parasitic capacitance increases causing performance deterioration
Solution Approach 1:
The patent introduces air sidewalls as intermediary structures between adjacent conductive structures. These air sidewalls act as dielectric spacers that electrically isolate the conductive structures while maintaining minimal physical distance, thus enabling high integration without increasing parasitic capacitance and preserving device performance
Data Source
AI summary
Embodiment relates to a semiconductor structure and a fabrication method thereof. The method for fabricating a semiconductor structure includes: providing a substrate including an array region and a peripheral region connected to the array region; arranging a plurality of pads on the array region, an isolation trench being formed between adjacent two of the plurality of pads; and forming a to-be-etched path layer on a sidewall of the isolation trench. In the method for fabricating a semiconductor structure, after the plurality of pads are formed, a to-be-etched path layer is formed on a sidewall of the isolation trench between the plurality of pads. The to-be-etched path layer may be in contact with a to-be-etched material layer in the array region. After a flat surface is formed on the array region and the peripheral region, the to-be-etched path layer and the to-be-etched material layer may be removed in sequence.