Isolation Trench Profile Control for GAA FET Fin Bases
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Solution Overview
Problem
The scaling down of semiconductor devices, such as GAA FETs, has increased the challenge of adequately removing semiconductor material from fin bases, leading to current leakage between adjacent source/drain regions, which degrades device performance and reliability.
Innovation Solution
A second isolation structure is formed by replacing a portion of the fin base with a dielectric material, using controlled plasma etching to create an isolation trench with specific cross-sectional profiles that ensure complete removal of the fin base material, preventing current leakage between source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance is improved, but current leakage between adjacent source/drain regions increases
Solution Approach 1:
The isolation structure is divided into multiple segments: a first isolation portion extending between gate structures, a second isolation portion extending between first isolation portions, a third isolation portion extending between second isolation portions, and a fourth isolation portion in the substrate. This segmented approach provides comprehensive electrical isolation at multiple levels, effectively preventing current leakage between adjacent source/drain regions while maintaining scaled dimensions.
Solution Approach 2:
The isolation structure extends in multiple spatial dimensions: vertically through the substrate (fourth isolation portion), horizontally between gate structures (first isolation portion), and at intermediate levels (second and third isolation portions). This multi-dimensional isolation architecture ensures complete electrical separation of adjacent devices, addressing the current leakage problem that arises from dimensional scaling.
2Reliability
If a second isolation structure is formed by replacing a portion of the fin base with dielectric material, then current leakage prevention is improved, but device complexity increases
Solution Approach 1:
The first, second, third, and fourth isolation portions are combined into a single integrated isolation structure formed by one continuous dielectric material filling a unified trench system. This merged structure provides comprehensive isolation functionality without requiring multiple separate fabrication steps or distinct structural components, thereby reducing overall device complexity while maintaining effective current leakage prevention.
Solution Approach 2:
The second isolation structure serves multiple functions simultaneously: it electrically isolates adjacent source/drain regions, provides mechanical support, and defines device boundaries. By consolidating these multiple functions into a single isolation structure, the patent avoids the complexity that would arise from implementing separate structures for each function.
3Manufacturing precision
If plasma etching is used to create an isolation trench with controlled profile, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
A mask structure is formed beforehand to define the isolation trench pattern before plasma etching. This preliminary masking action controls the trench profile and ensures precise positioning of the isolation structure, while the mask itself is formed using standard photolithography techniques rather than complex direct-write methods.
Solution Approach 2:
The plasma etching process replaces mechanical or chemical etching methods to create the isolation trench. Plasma etching provides superior profile control and anisotropy, enabling precise trench formation with vertical sidewalls and accurate depth control, while being integrated into existing semiconductor fabrication workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes current leakage and enhances the performance and reliability of GAA FETs by ensuring adequate electrical isolation between source/drain regions.
Implementation Method 1
By controlling the plasma etching process parameters (e.g., etching gas type, etching gas flow rate, processing chamber pressure, bias power, etc.), the profile of the isolation trench can be controlled to ensure adequate removal of the portion of the fin base.
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured layers on first and second fin bases, forming cladding layers on sidewalls of the first and second nanostructured layers, forming a polysilicon structure on the first and second nanostructured layers, removing a portion of the polysilicon structure to form a first opening on the second nanostructured layers, removing a portion of the second nanostructured layers through the first opening to form a second opening on the second fin base, removing a portion of the second fin base through the second opening to form a third opening on the substrate, removing a portion of the substrate through the third opening to form a fourth opening in the substrate, and depositing an insulation material to fill the first, second, third, and fourth openings.