Semiconductor Isolation Structure With Nested Vertical Interconnects
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, such as MOSFETs, finFETs, and GAA FETs, necessitating a solution to enhance device density without compromising electrical isolation and requiring fewer process steps.
Innovation Solution
The implementation of stacked FETs with vertical interconnect structures and isolation structures formed in a cut-metal-gate process, which reduces device area occupation and resistance by integrating vertical interconnects within isolation structures, using a single photolithographic and etch process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional isolation structures are used between FETs, then electrical isolation is maintained, but device density is reduced and manufacturing complexity increases
Solution Approach 1:
The patent combines the isolation structure and vertical interconnect structure into a single integrated formation process. The isolation trench is formed, then filled with dielectric material and conductive material in sequence, creating both the isolation barrier and the vertical interconnect pathway simultaneously. This merging eliminates the need for separate processing steps for isolation and interconnect formation, thereby increasing device density while reducing manufacturing complexity.
Solution Approach 2:
The isolation structure serves multiple functions: it provides electrical isolation between adjacent FETs, acts as a support structure for vertical interconnects, and enables compact device layout. By designing the isolation structure to simultaneously fulfill isolation and interconnect support roles, the patent achieves multi-functionality that increases device density without adding manufacturing steps.
2Reliability
If vertical interconnect structures are formed adjacent to isolation structures, then electrical isolation is maintained, but device area occupation increases and resistance is higher
Solution Approach 1:
The patent places the vertical interconnect structure inside the isolation structure, with the conductive material nested within the dielectric-filled isolation trench. This nesting arrangement allows the vertical interconnect to occupy the same spatial envelope as the isolation structure, eliminating the need for additional area adjacent to the isolation structure. The electrical isolation is maintained because the dielectric material surrounds the conductive interconnect, preventing current leakage while minimizing device area occupation.
3Manufacturing precision
If multiple process steps are used for isolation and interconnect formation, then manufacturing precision is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent merges the isolation formation and vertical interconnect formation into a single integrated process sequence. The isolation trench is formed first, then dielectric material is deposited to fill the trench, followed by conductive material deposition to form the vertical interconnect. This combined approach maintains manufacturing precision because each material is deposited with controlled thickness and composition, while reducing manufacturing cost and complexity by eliminating separate processing cycles for isolation and interconnect formation.
4Productivity
If FETs are scaled down to increase device density, then storage capacity and processing speed improve, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar interconnect structures to vertical interconnect structures, utilizing the vertical dimension to provide electrical connections. This dimensional change allows for compact device layouts with scaled-down FETs, as the vertical interconnects occupy minimal horizontal space while providing efficient electrical pathways. The integrated formation process with isolation structures ensures that this dimensional transition does not increase manufacturing complexity, thereby enabling higher device density, storage capacity, and processing speed.
Data Source
AI summary
A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.