Isolation Walls for Vertically Stacked Transistors
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Solution Overview
Problem
Integration of vertically stacked transistor structures in integrated circuits faces challenges with high gate capacitance, leading to increased power consumption and reduced switching speed, particularly when uniform-sized isolation walls are used between transistors of different sizes or shapes.
Innovation Solution
Implementing isolation walls with varying widths and shapes that match the contours of the transistor structures at different device layers, ensuring equal gate widths to minimize gate capacitance and facilitate easier lithographic registration during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform-sized isolation walls are used between vertically stacked transistor structures, then fabrication is simplified, but gate capacitance increases leading to higher power consumption and reduced switching speed
Solution Approach 1:
The isolation walls are designed with varying widths at different horizontal positions rather than uniform width throughout. The first width at the first horizontal position differs from the second width at the second horizontal position, allowing local optimization of gate capacitance while maintaining fabrication feasibility through defined geometric variations.
2Ease of manufacture
If uniform-sized isolation walls are used between vertically stacked transistor structures, then fabrication is simplified, but switching speed decreases due to increased gate capacitance
Solution Approach 1:
The isolation walls implement non-uniform width distribution where the first width at the first horizontal position is optimized for one aspect and the second width at the second horizontal position is optimized for another, thereby reducing overall gate capacitance and improving switching speed while maintaining manufacturability.
3Use of energy by moving object
If isolation walls have varying widths to match transistor contours, then gate capacitance is reduced, but fabrication precision requirements increase
Solution Approach 1:
The isolation walls deliberately employ asymmetric width variation between different horizontal positions and between adjacent isolation walls. This asymmetric design reduces gate capacitance by matching the contours of adjacent transistor structures while the variations are controlled to remain within lithographic fabrication capabilities.
Data Source
AI summary
Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.