Galvanic Isolation Wire Bond Layout for Encapsulant Field Stress
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Solution Overview
Problem
Galvanic isolation devices face challenges in providing reliable electrical connections while minimizing electric field stress on encapsulant material and meeting package dimensional constraints, particularly due to the risk of damage from electric field-induced voids or defects in the encapsulant material.
Innovation Solution
The microelectronic device incorporates a galvanic isolation component with a lower isolation element and dielectric plateau, featuring high voltage wire bonds that extend vertically with a deviation angle of 10 degrees and low voltage wire bonds with a loop height less than 5 times their diameter, ensuring adequate separation and reducing electric field stress through specific wire bonding methods and encapsulant material composition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect galvanic isolation devices in multi-chip modules, then reliable electrical connections are achieved, but electric field stress on encapsulant material increases causing potential damage from electric field-induced voids or defects
Solution Approach 1:
The patent divides the wire bond structure into two distinct types: high voltage wire bonds that extend vertically for a distance greater than the isolation distance between voltage domains, and low voltage wire bonds that form loops with height less than 5 times the wire diameter. This segmentation allows each wire bond type to be optimized for its specific voltage domain, reducing overall electric field stress on the encapsulant material while maintaining reliable electrical connections.
Solution Approach 2:
The patent introduces vertical dimension control as a key parameter for wire bond configuration. High voltage wire bonds extend vertically upward within 10 degrees of vertical for a distance greater than the isolation distance, effectively using the vertical dimension to achieve electrical isolation. This dimensional approach creates natural electric field management without requiring additional isolation structures.
2Object-affected harmful factors
If high voltage wire bonds extend vertically for isolation, then electric field stress is reduced, but package dimensional constraints become more difficult to meet
Solution Approach 1:
The patent applies different wire bond configuration strategies to different locations and voltage domains within the package. High voltage wire bonds use vertical extension beyond the isolation distance, while low voltage wire bonds use compact loops. This localized quality approach ensures that vertical extension is applied only where necessary for high voltage isolation, minimizing the impact on overall package dimensions while still achieving electric field stress reduction.
3Ease of manufacture
If low voltage wire bonds have large loop heights, then ease of manufacturing is improved, but electric field stress on encapsulant material increases
Solution Approach 1:
The patent establishes specific parameter thresholds for wire bond dimensions: low voltage wire bonds must have loop heights less than 5 times the wire diameter, and high voltage wire bonds must extend vertically within 10 degrees of vertical for a distance greater than the isolation distance. These parameter changes create clear manufacturing specifications that balance ease of fabrication with electric field stress reduction, making the design rules both manufacturable and effective.
Data Source
AI summary
A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.