Digital Isolator Capacitor Layout for Higher Breakdown Voltage

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Solution Overview

Problem

The challenge in semiconductor devices with digital isolators is the occurrence of dielectric breakdown due to high voltage application, which is exacerbated by sharp corners and potential differences leading to leakage currents and reduced dielectric strength, particularly in materials like passivation films and molding compounds.

Innovation Solution

The semiconductor device design incorporates a top electrode with rounded corners and a recessed third inter-metal dielectric film, along with a passivation film, to disperse electric fields and enhance dielectric strength, using etching processes like sputter etching and chemical mechanical polishing to shape the electrodes and metal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a wide gap exists between top metal and top electrode, then leakage current is reduced, but device size increases

Engineering Contradiction:
Improveleakage currentVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The top corner of the top electrode is formed with a rounded shape instead of a sharp corner. This curvature distributes the electric field more evenly, preventing concentration at the corner and reducing leakage current without requiring a wide gap between the top metal and top electrode, thus maintaining compact device size

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Power

If high voltage is applied to conductor structure with sharp edge, then electric field concentrates to layer around sharp edge, but dielectric breakdown occurs

Engineering Contradiction:
ImprovevoltageVSAvoiddielectric breakdown
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The top corner of the top electrode is rounded to distribute the electric field evenly across the surface, preventing concentration at sharp edges and eliminating the condition that leads to dielectric breakdown under high voltage application

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Power

If voltage is increased in digital isolator, then it is easier for leakage current to occur, but digital isolator performance is improved

Engineering Contradiction:
ImprovevoltageVSAvoidleakage current
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The rounded top corner of the top electrode distributes the electric field, allowing high voltage to be applied without creating concentrated field regions that would cause leakage current, thus enabling both high voltage operation and low leakage current

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design increases breakdown voltage and reduces the likelihood of dielectric breakdown, maintaining high withstand voltage characteristics without increasing device size, while ensuring efficient electrical connectivity and insulation.

Implementation Method 1

the top electrode is configured to have a rounded top corner... an electric field may be concentrated to a layer around a sharp edge... to disperse electric fields

Methodology Applied
Scientific EffectElectric field dispersion: Electric Field

Implementation Method 2

using etching processes like sputter etching and chemical mechanical polishing to shape the electrodes and metal lines

Methodology Applied
Scientific EffectSputter etching: Sputtering

Implementation Method 3

using etching processes like sputter etching and chemical mechanical polishing to shape the electrodes and metal lines

Methodology Applied
Scientific EffectChemical mechanical polishing:

Data Source

PatentUS12464736B2Semiconductor device with digital isolator capacitor and manufacturing method thereof
Publication Date: 2025.11.04 SK KEYFOUNDRY INC
  • US12464736B2 patent drawing
  • US12464736B2 patent drawing
  • US12464736B2 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes a logic region and a capacitor region, wherein the capacitor region comprises a bottom electrode disposed on a substrate; a top electrode disposed on the bottom electrode; a first inter-metal dielectric film disposed between the substrate and the bottom electrode; a second inter-metal dielectric film and a third inter-metal dielectric film disposed between the top electrode and the bottom electrode; a passivation film disposed on the top electrode, wherein the top electrode is configured to have a rounded top corner, and the bottom electrode is configured to have a sharp top corner.