Two-Die Isolator Link With Tapped Impedance for High CMTI
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Solution Overview
Problem
Conventional on-chip isolator devices face a trade-off between high common-mode transient immunity (CMTI) and gain, and are unsuitable for high-power applications due to incompatibility with semiconductor processes used for large wafer fabrication, particularly when using materials like polyimide for isolation barriers.
Innovation Solution
A two-die isolator design is employed, where one die supports an isolation barrier and the other is barrierless, equipped with a tapped impedance element coupled to a reference potential, providing a discharge path for common-mode transients, enhancing CMTI without sacrificing gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation barrier is formed on both dies using materials like polyimide, then galvanic isolation and safety are improved, but compatibility with semiconductor processes for large wafer fabrication is lost
Solution Approach 1:
The isolator device is divided into two separate dies: a first die with an isolation barrier for galvanic isolation, and a second barrierless die for high-power semiconductor processing. This segmentation allows each die to be optimized for its specific function - the first die provides safety and isolation while the second die maintains compatibility with standard semiconductor fabrication processes for large wafers.
2Ease of manufacture
If a barrierless second die is used for high-power applications, then semiconductor process compatibility is improved, but common-mode transient immunity is degraded
Solution Approach 1:
A tapped impedance element is introduced as an intermediary between the isolation barrier and the barrierless die. This impedance element with its tap to reference potential acts as a mediator that provides a controlled discharge path for common-mode transients, protecting the barrierless die from transient effects while maintaining compatibility with high-power semiconductor processes.
3Object-affected harmful factors
If the secondary side is coupled to a tapped impedance element, then common-mode transient immunity is improved, but device complexity increases
Solution Approach 1:
The impedance element's parameters (impedance value, tap position) are optimized to provide effective common-mode transient discharge paths without requiring complex additional circuitry. By carefully selecting and tuning these parameters, the design achieves high CMTI performance while maintaining relatively simple device structure and fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves CMTI exceeding 100 kV/µs while maintaining high gain, suitable for high-power applications such as motor drivers, by leveraging different semiconductor processes for each die.
Implementation Method 1
the second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.
Data Source
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Figure 2A~2C
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AI summary
Described herein are on-chip isolator devices that can be employed in high-power applications and that are designed to enhance high common-mode transient immunity (CMTI) without sacrificing isolator gain. An isolator device includes two dies. A first die supports an isolation barrier and the second die is barrierless. The second die is barrierless in that it lacks isolation materials that are commonly used to sustain isolation barriers in on-chip isolator devices (e.g., polyimide). To enhance CMTI despite the absence of a further isolation barrier formed on the second die, the second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.