Isolator Symmetric Terminal Layout for Common Mode Transient Immunity
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Solution Overview
Problem
Isolation communication channels across voltage barriers are susceptible to common mode transients, which interfere with signal accuracy due to parasitic capacitance mismatches between terminals in differential pairs, limiting immunity to noise and transient events.
Innovation Solution
An integrated circuit design with symmetric terminal layouts and parasitic capacitance matching, where additional dummy terminals are used to ensure that each terminal in a differential pair has substantially the same parasitic capacitance, reducing differences and improving common mode transient immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asymmetric terminal layout is used in conventional isolators, then manufacturing is simpler, but parasitic capacitance mismatch occurs between differential pair terminals reducing common mode transient immunity
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately creates a symmetric terminal layout where terminals that would naturally be asymmetric are made symmetric through dummy terminals and adjusted spacing. This symmetry ensures equal parasitic capacitance values for both terminals in a differential pair, improving common mode transient immunity by eliminating capacitance mismatch.
Solution Approach 2:
The patent applies local quality by making specific local adjustments to the terminal layout - adding dummy terminals next to certain terminals and adjusting the spacing between specific terminals. These localized modifications ensure that each terminal in a differential pair has substantially equal parasitic capacitance, while other parts of the device can maintain their original design.
2Measurement precision
If symmetric terminal layout with dummy terminals is implemented, then parasitic capacitance matching is achieved, but device area and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by making specific local adjustments to the terminal layout - adding dummy terminals next to certain terminals and adjusting the spacing between specific terminals. These localized modifications ensure that each terminal in a differential pair has substantially equal parasitic capacitance, while other parts of the device can maintain their original design.
Solution Approach 2:
The patent applies partial action by adding only the minimum necessary dummy terminals and spacing adjustments required to achieve capacitance matching, rather than making the entire terminal layout symmetric. This partial approach achieves the necessary precision for differential signal resolution while minimizing the additional area required.
3Area of stationary object
If terminals are placed closer together to reduce area, then device size decreases, but parasitic capacitance control and signal integrity deteriorate
Solution Approach 1:
The patent applies local quality by making specific local adjustments to the terminal layout - adding dummy terminals next to certain terminals and adjusting the spacing between specific terminals. These localized modifications ensure that each terminal in a differential pair has substantially equal parasitic capacitance, while other parts of the device can maintain their original design.
Solution Approach 2:
The patent applies parameter changes by adjusting the physical spacing between terminals and adding dummy terminals to modify the parasitic capacitance values. These parameter adjustments allow for precise control of capacitance matching while maintaining compact overall device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The symmetric terminal layout enhances the isolator's immunity to common mode transients, allowing it to effectively communicate signals across large voltage differences without compromising differential signal resolution, achieving common mode transient immunity of at least 100 kV/μs.
Implementation Method 1
an intermediate system includes isolation that prevents damaging currents from flowing between the processor system and the load system. Although the isolation prevents the processor system from being coupled to the load by a direct conduction path, an isolation communications channel allows communication between the two systems
Implementation Method 2
The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance.
Data Source
AI summary
An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.