Self-Aligned Isotropic Etch for BEOL Via Patterning
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Solution Overview
Problem
The scaling of features in integrated circuits poses challenges in achieving precise overlay and critical dimension control for vias and interconnects, particularly at pitches below 70 nanometers, where lithographic equipment resolution limits and line width roughness/critical dimension uniformity issues hinder efficient fabrication.
Innovation Solution
A self-aligned isotropic etch process is employed for via and plug patterning, using pre-formed structures and sacrificial placeholder materials, allowing for selective etching and reduced alignment reliance, thereby improving overlay margins and patterning resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic processes are used to pattern vias at small pitches, then via density increases, but overlay precision deteriorates due to equipment resolution limits
Solution Approach 1:
The patent applies preliminary action by pre-forming placeholder structures (mandrels) at all potential via locations before the actual via patterning step. This allows the subsequent lithographic process to only need to define which placeholders to remove, rather than defining via locations from scratch, thereby reducing overlay requirements and improving precision at high via densities
Solution Approach 2:
The patent introduces placeholder structures as intermediary elements that mediate between the lithographic patterning process and the final via formation. These placeholders serve as temporary structures that simplify the lithographic step, allowing indirect definition of via locations through selective removal rather than direct patterning, thus overcoming resolution limits
2Length of moving object
If via critical dimensions are reduced to increase density, then via pitch decreases, but line width roughness and critical dimension uniformity deteriorate
Solution Approach 1:
The patent applies self-service through self-aligned isotropic etching where the etch process automatically maintains uniform via dimensions by etching equally in all directions from the placeholder structures. The process self-regulates to maintain critical dimension uniformity without requiring complex process control, as the isotropic nature of the etch ensures consistent material removal regardless of slight variations in placeholder dimensions
3Manufacturing precision
If multiple lithographic masks are used to achieve small via pitches, then patterning capability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses preliminary action by pre-forming placeholder structures that encode potential via locations, allowing a single lithographic step to define the actual via pattern by selective removal. This eliminates the need for multiple sequential lithographic masks and alignment steps, significantly simplifying the manufacturing process while maintaining high patterning resolution
Solution Approach 2:
The patent applies taking out by extracting the via location definition from the main lithographic patterning step and separating it into a preliminary placeholder formation step. The actual via pattern is then obtained by removing specific placeholders rather than directly patterning, thereby simplifying the complex multi-mask lithographic process into a single effective patterning step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and accuracy of interconnect fabrication by minimizing the size and shape of required patterns, reducing alignment complexities, and lowering equipment costs, while maintaining electrical contact quality.
Implementation Method 1
subsequently removing the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches, thereby self-aligned isotropically re-exposing holes or trenches at the via locations
Data Source
AI summary
Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.