3D Transistor Fabrication via Isotropic Etching Undercut
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in achieving high integration while maintaining performance and integrity, particularly in forming three-dimensional structures and fully surrounded transistor structures.
Innovation Solution
The method involves forming pair of openings in a semiconductor material with liners along the sidewalls, followed by isotropic etching to merge these openings and undercut the semiconductor material, allowing for the creation of three-dimensional structures and SOI constructions by filling the openings with insulative material or transistor gate material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication techniques are used, then manufacturing simplicity is maintained, but integration density and device performance deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional device structures to three-dimensional structures by forming openings that extend through the substrate and merging them via isotropic etching. This dimensional change enables fully surrounded transistor structures and SOI constructions that wrap around active regions, significantly increasing integration density without proportionally increasing process complexity.
Solution Approach 2:
The fabrication process segments the formation of three-dimensional structures into distinct stages: first forming separate openings with liners, then merging them through isotropic etching, and finally filling with appropriate materials. This segmentation allows complex 3D structures to be built using standard process steps applied in sequence, managing complexity while achieving high integration.
2Reliability
If three-dimensional structures are formed, then device performance and integration are improved, but manufacturing complexity increases
Solution Approach 1:
The isotropic etching step serves multiple functions simultaneously: it merges adjacent openings to create fully surrounded structures, defines the three-dimensional geometry of the active regions, and prepares the surfaces for subsequent material filling. This multi-functionality reduces the number of specialized process steps needed, easing manufacturing while achieving complex 3D structures.
Solution Approach 2:
Liners are formed as intermediary structures along the sidewalls of openings before the isotropic etching step. These liners protect the sidewalls during etching, control the merging process, and provide a foundation for subsequent material deposition. The liners act as a mediator that enables precise control of the three-dimensional structure formation without requiring entirely new fabrication techniques.
3Area of stationary object
If wafer real estate is conserved, then integration density increases, but maintaining device integrity becomes more difficult
Solution Approach 1:
The patent creates nested structures where insulative material or gate material is filled within the merged openings, which themselves are formed around semiconductor active regions. This nesting arrangement allows multiple functional layers to occupy the same vertical space, conserving wafer real estate while maintaining clear separation and integrity of each device component through the layered nested construction.
Solution Approach 2:
The device structures comprise composite materials including semiconductor material, insulative material, conductive gate material, and liner materials all integrated within the same three-dimensional structure. This composite approach allows each material to perform its specific function while being tightly integrated, maintaining device integrity despite high integration density achieved through conservative wafer real estate utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-integration semiconductor devices with improved performance by creating fully surrounded transistor structures and SOI constructions, enhancing the semiconductor wafer real estate utilization.
Implementation Method 1
the semiconductor material is isotropically etched from bottoms of the lined openings to merge the openings and thereby completely undercut the segment of semiconductor material
Data Source
AI summary
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.