Isotropic Gate Etch for Vertical FET Channel Length Control
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Solution Overview
Problem
Vertical FET architecture faces challenges in precise control of channel length due to spatial variability in gate conductor removal rates caused by local pattern density and loading effects, leading to inconsistent device performance.
Innovation Solution
A method involving an isotropic etch of the gate conductor to recess the gate and define the channel length, ensuring a symmetric pre-etch gate conductor geometry decouples the etch rate from adjacent structures, resulting in uniform channel lengths across multiple fins, compatible with existing circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic etching is used to remove gate conductor, then channel length can be defined, but spatial variability in removal rate due to pattern density causes poor manufacturing precision
Solution Approach 1:
The patent changes the etching parameter from anisotropic to isotropic, fundamentally altering the removal mechanism. This parameter change eliminates the directional dependency that causes pattern density effects, achieving uniform channel length (20-30nm) across diverse device layouts with variability reduced to less than 10%
Solution Approach 2:
The patent replaces the mechanical/physical anisotropic etching process with an isotropic chemical etching process. This substitution changes the fundamental mechanism from direction-dependent physical sputtering to direction-independent chemical dissolution, eliminating the loading effects that plague anisotropic approaches
2Manufacturing precision
If gate conductor thickness varies to match inter-fin spacing, then etch rate uniformity improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by making the gate conductor thickness position-dependent, specifically matching the thickness to the inter-fin spacing at each location. This local adaptation ensures that the isotropic etch removes material uniformly across regions with different fin densities, achieving consistent channel lengths without requiring global geometry changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of top spacers and epitaxial raised active regions for source/drain contacts, achieving channel length uniformity of less than 10% variability across multiple devices, enhancing manufacturing robustness and precision.
Implementation Method 1
performing an isotropic etch of the gate conductor to recess the gate and define the length of the channel
Data Source
AI summary
A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.