Image Signal Processor Deferred Vertical Sync Output

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Solution Overview

Problem

Conventional imaging devices face issues with incorrect encoding and data transfer due to the timing of vertical synchronous signals, leading to errors in image data processing and incomplete encoding of frames.

Innovation Solution

The method involves delayed transfer of vertical synchronous signals and the use of an image signal processor to control the output of encoded data, ensuring that the input of processed data for the current frame is not interfered with by the new frame signal, and allowing for optimal hardware design and control through a general interface structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the vertical synchronous signal is transferred immediately upon receiving a new frame, then the response time is reduced, but encoding errors occur and data transfer accuracy deteriorates

Engineering Contradiction:

Improveresponse timeVSAvoiddata transfer accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting the vertical synchronous signal in advance and holding it in a buffer before transferring. This allows the system to prepare for the next frame reception without immediately transferring data, preventing encoding errors while maintaining timely response through buffered data availability.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If encoding is performed continuously without frame completion verification, then processing speed is improved, but encoding completeness and reliability deteriorate

Engineering Contradiction:

Improveprocessing speedVSAvoidencoding completeness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback by continuously monitoring whether frame encoding is complete before transferring the vertical synchronous signal. This feedback mechanism ensures that data is only transferred when encoding is verified as complete, maintaining reliability while enabling continuous processing of subsequent frames.

Inventive Principle:

Principle #23Feedback

3Productivity

If the back-end chip processes data immediately upon receipt, then processing efficiency is improved, but power consumption increases due to premature processing

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by having the image signal processor prepare and buffer the vertical synchronous signal and encoded data before transferring to the back-end chip. This allows the back-end chip to process data at optimal times when data is ready and valid, improving efficiency while reducing power consumption by avoiding premature or redundant processing operations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8154749B2Image signal processor and deferred vertical synchronous signal outputting method

Publication Date: 2012.04.10 MILA US INC

AI summary

A method of transferring a deferred vertical synchronous signal and an image signal processor executing the method thereof are disclosed. Once the vertical synchronous signal for a kth frame is inputted from an encoding unit after a capture command is inputted, the method transmits a defer control command for a (k+1)th frame to an image sensor. Then, a return control command is transmitted to the image sensor if encoding of the kth frame is completed. With the present invention, complete encoding of image data becomes possible.