Image Processing Apparatus Vertical Blanking Period Synthesis
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Solution Overview
Problem
In image processing apparatuses with multiple virtual channels, securing vertical blanking periods for normal diagnosis is challenging, making it difficult to perform built-in self tests on image signal processors (ISPs) that process data from multiple cameras.
Innovation Solution
The apparatus includes a data storage unit, an image processing processor, and a test circuit, where image data from multiple cameras are assigned to transfer units and stored in a buffer, allowing phases to be matched and securing vertical blanking periods for built-in self testing of the ISP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple virtual channels are used to transmit image data from multiple cameras, then the image processing capability is improved, but it becomes difficult to secure vertical blanking periods for normal diagnosis
Solution Approach 1:
A buffer is introduced as an intermediary component between the virtual channels and the image signal processor. The buffer stores image data from multiple VCs and generates a synthesized vertical blanking period by combining blanking period signals from individual channels, enabling BIST functionality without disrupting the multi-VC image processing workflow
2Reliability
If vertical blanking periods are secured for built-in self testing, then the reliability of ISP is improved, but the time availability for image processing is reduced
Solution Approach 1:
The system implements periodic built-in self testing during synthesized vertical blanking periods while maintaining continuous image processing during active periods. The buffer synchronizes multiple image data streams to create periodic opportunities for BIST without interrupting the overall image processing workflow
Solution Approach 2:
The buffer pre-processes and stores image data from multiple virtual channels, preparing synthesized vertical blanking period signals in advance. This preliminary action enables the ISP to perform BIST during predetermined intervals without disrupting the real-time image processing pipeline
Data Source
AI summary
An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.