Non-Volatile Memory Programming via ISPP and Current Sensing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory devices face challenges in improving data input/output speed and reducing the operational burden on non-volatile memory cells, which leads to increased wear and interference between cells during programming operations.

Innovation Solution

The implementation of an Incremental Step Pulse Programming (ISPP) method that dynamically allocates data paths and uses a current sensing circuit to optimize program loops, allowing for reduced verification operations and a narrower threshold voltage distribution, thereby enhancing data safety and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional programming methods are used to store data in non-volatile memory cells, then data can be stored, but the threshold voltage distribution becomes wide causing interference between adjacent cells and increasing operational burden

Engineering Contradiction:
Improvedata safetyVSAvoidinterference between cells
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the programming process adaptive through incremental step pulse programming. The program voltage is dynamically adjusted in multiple stages with verification steps, allowing the system to adapt to the actual state of memory cells during programming. This dynamic approach narrows the threshold voltage distribution by precisely controlling the programming voltage levels, thereby reducing interference between adjacent cells while maintaining data safety.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent utilizes parameter changes by modifying the program voltage parameters through incremental steps. Instead of applying a single fixed voltage, the system varies the program voltage across multiple levels (e.g., from lower to higher voltages in stages) and adjusts pulse widths. This parameter optimization narrows the threshold voltage distribution, reducing cell-to-cell interference while ensuring reliable data storage.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple verification operations are performed to ensure accurate data storage, then data safety improves, but programming time and operational complexity increase

Engineering Contradiction:
Improvedata storage accuracyVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing verification operations at strategic intermediate points during the incremental programming process. Rather than waiting until the end, the system verifies data accuracy after certain programming stages, allowing early detection of programming failures and preventing wasted time on completely failed programming operations. This staged verification approach balances data safety with time efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements skipping by conditionally bypassing certain verification steps based on previous verification results. When verification indicates successful programming, the system can skip redundant verification operations and proceed directly to the next programming task. This selective approach maintains data accuracy while significantly reducing unnecessary programming time and operational complexity.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If programming operations are performed frequently to update data, then data freshness improves, but wear on non-volatile memory cells increases reducing device lifespan

Engineering Contradiction:
Improvedata freshnessVSAvoidmemory cell lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies partial action by performing programming operations only when necessary and only to the extent required. The incremental step pulse programming method allows the system to program memory cells in controlled stages, applying the minimum necessary voltage and time to achieve successful programming. This reduces the total stress on memory cells compared to aggressive programming methods, thereby extending device lifespan while maintaining data freshness.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent utilizes periodic action by implementing programming operations at optimized intervals rather than continuously. The system performs programming only when data updates are required, with verification steps ensuring successful programming before proceeding. This periodic, on-demand approach reduces the frequency of programming operations, minimizing wear on memory cells while maintaining up-to-date data storage.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances data input/output speed, reduces wear on non-volatile memory cells, and improves data safety by minimizing interference and operational burden, while maintaining a narrow threshold voltage distribution for accurate data storage.

Implementation Method 1

a current sensing circuit for detecting whether a threshold voltage distribution of the plurality of non-volatile memory cells satisfies a reference

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11887669B2Apparatus and method for programming data in a non-volatile memory device
Publication Date: 2024.01.30 SK HYNIX INC
  • US11887669B2 patent drawing
  • US11887669B2 patent drawing
  • US11887669B2 patent drawing

AI summary

A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.