ISPP Programming Method for Non-Volatile Memory Devices
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Solution Overview
Problem
Conventional incremental step pulse programming (ISPP) schemes in non-volatile memory devices often cause program disturbs due to high program voltages, which undesirably modify the threshold voltages of adjacent memory cells, leading to data reliability issues.
Innovation Solution
A method that alternates between two program modes: a first mode with constant pulse width and incrementally increasing program voltage, and a second mode with incrementally increasing pulse width and constant program voltage, or a mode where the program voltage is maintained at a maximum value, to reduce the risk of program disturbs by controlling the pulse width and voltage increments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program voltage is successively increased per ISPP cycle with constant pulse width, then programming speed is improved, but program disturb in adjacent memory cells increases
Solution Approach 1:
The patent applies periodic action by alternating between two program modes in a cyclic manner. The controller switches between first program mode (constant pulse width, increasing voltage) and second program mode (increasing pulse width, constant voltage) to periodically vary the programming conditions. This periodic variation prevents continuous high-voltage stress on adjacent cells while maintaining overall programming progress, thereby reducing program disturb effects.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting both pulse width and program voltage based on the current programming stage and verification results. In the first program mode, voltage is increased while pulse width remains constant; in the second program mode, pulse width is increased while voltage is held constant. This dynamic parameter adjustment optimizes the balance between programming efficiency and disturbance reduction.
2Manufacturing precision
If program voltage is increased to properly program target memory cell, then programming effectiveness is improved, but threshold voltage of adjacent memory cells is undesirably modified
Solution Approach 1:
The patent segments the programming process into two distinct modes with different characteristics. The first program mode focuses on voltage incrementation for effective programming, while the second program mode focuses on pulse width extension with constant voltage to reduce disturbance. By dividing the programming process into these segments, the patent achieves both programming effectiveness and data reliability.
Solution Approach 2:
The controller periodically switches between the two program modes based on verification results and programming progress. This periodic action ensures that high-voltage programming is interspersed with lower-disturbance modes, preventing cumulative damage to adjacent cells while maintaining overall programming effectiveness.
3Measurement precision
If ISPP scheme is used to incrementally define threshold voltage, then programming control is improved, but risk of program disturb increases
Solution Approach 1:
The patent introduces dynamics by making the programming parameters (pulse width and voltage) adaptive rather than static. The controller dynamically selects between first and second program modes based on real-time verification results and programming progress. This dynamic adaptation allows the system to maintain precise threshold voltage control while minimizing program disturb risk through flexible parameter adjustment.
Solution Approach 2:
The patent implements parameter changes by varying both pulse width and voltage based on the current programming state. The system transitions from voltage-increment mode to pulse-width-increment mode and back, creating a dynamic parameter profile that optimizes the balance between control precision and disturbance reduction.
Data Source
AI summary
A method programming a non-volatile memory device using an incremental step pulse programming (ISPP) scheme is disclosed. The method includes operating in a first program mode during which a program pulse width is constant and a program voltage is successively increased per ISPP cycle, and during which a program operation and a verify operation are alternately repeated, and operating in a second program mode during which the program pulse width is successively increased per ISPP cycle and the program voltage is constant, and during which the program operation and the verify operation are alternately repeated, wherein operation in the second program mode follows operation in the first program mode only when the program voltage equals a maximum value, or when a verification result count value satisfies a predetermined condition.