ISR Packet Protocol for CRC Integrity and Time Synchronization

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Solution Overview

Problem

ISR systems face limitations in data integrity and time synchronization due to physical network interface restrictions and non-standard processor configurations, which hinder the use of common architectural elements and algorithms across multiple airborne platforms.

Innovation Solution

A multi-processor computer system with a remote node and control node, utilizing co-processors for data acquisition and analysis, packet headers with CRC values for integrity verification, and high-speed serial interfaces for synchronization, enabling data integrity and time synchronization across multi-domain operational platforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If physical network interfaces are used to connect processors, then data transmission can be achieved, but the available locations of processors are restricted and timing synchronization is limited

Engineering Contradiction:
Improveprocessor location flexibilityVSAvoidnetwork interface constraints
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The packet protocol is designed to be universally applicable across different processor architectures and network configurations. The standardized packet format with universal headers (timestamps, CRC, control data) enables the same communication mechanism to work across diverse platforms, eliminating the need for platform-specific adaptations and thereby achieving processor location flexibility without being constrained by specific network interface implementations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If non-standard processor configurations are used, then platform-specific optimizations are possible, but common architectural elements and algorithms cannot be used

Engineering Contradiction:
Improveplatform optimizationVSAvoidarchitectural compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system enforces homogeneity in the communication protocol layer by using standardized packet formats, fixed field structures, and uniform CRC calculation methods across all processors. This homogeneous approach to data communication enables different processor configurations to interoperate seamlessly, allowing platform-specific optimizations at the hardware level while maintaining architectural compatibility through the standardized protocol interface.

Inventive Principle:
Principle #33Homogeneity

3Reliability

If data is transmitted without integrity verification, then transmission speed is faster, but data integrity cannot be ensured

Engineering Contradiction:
Improvedata integrityVSAvoidintegrity verification overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The CRC (Cyclic Redundancy Check) value acts as an intermediary mechanism for integrity verification. Instead of complex error detection algorithms, the system uses the compact CRC checksum as a mediator to verify data integrity efficiently. The CRC value is calculated from the control data and transmitted alongside it, providing reliable integrity checking with minimal computational overhead, thus ensuring data reliability without significantly increasing system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Loss of time

If timestamps are not included in packets, then packet size is smaller, but time synchronization cannot be achieved

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidpacket data volume
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The packet protocol includes only the essential timestamp fields needed for synchronization without adding excessive time-related data. The master timestamp and remote timestamp fields provide sufficient information for time synchronization while keeping the packet size manageable. This partial inclusion approach achieves the necessary synchronization accuracy without the overhead of comprehensive time-stamping mechanisms, balancing synchronization needs against packet size constraints.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10411793B1Data transport and time synchronization for ISR systems
Publication Date: 2019.09.10 GOODRICH CORP
  • US10411793B1 patent drawing
  • US10411793B1 patent drawing
  • US10411793B1 patent drawing

AI summary

A computer system is provided that includes devices configured to acquire input data. The system further includes a remote node (RN) configured to receive a first packet from a control node (CN). The first packet includes a packet header including a master timestamp, first control data and a CRC. The RN is also configured to verify integrity of the first control data based on the received CRC, generate and transmit to the CN a second packet. The second packet includes a packet header which includes a remote timestamp. The system also includes a CN connected with the RN via high-speed serial interfaces. The CN is configured to receive the second packet, determine status of the first packet based on the control data included in the second packet and configured to retransmit the first packet or generate and transmit a third packet based on the determined status of the first packet.